Backend design of modern VLSI circuits includes critical steps like physical design, physical verification, and mask synthesis in the design flow. With continuous increase of design complexity, backend design becomes extremely challenging and time-consuming due to the repeated design iterations for the optimization of performance, power, area, and manufacturability. With recent boom of artificial intelligence, deep learning has shown its potential in various fields, like computer vision, recommendation systems, robotics, etc. Incorporating deep learning into the VLSI design flow has also become a promising trend. In this talk, we will introduce our recent studies on developing dedicated deep learning techniques for cross-stage modeling and optimization in backend design. We will also discuss the impact of large-scale and diverse datasets (e.g., CircuitNet) on improving the performance of deep learning models.

 Speaker Bio:  

Dr. Yibo Lin is an Assistant Professor in the School of Integrated Circuits at Peking University. He received the B.S. degree in microelectronics from Shanghai Jiaotong University in 2013, and his Ph.D. degree from the Electrical and Computer Engineering Department of the University of Texas at Austin in 2018. His research interests include physical design, machine learning applications, and GPU/FPGA acceleration. He has received 6 Best Paper Awards at premier venues including DATE 2022, TCAD 2021, and DAC 2019. He has also served in the Technical Program Committees of many major conferences, including ICCAD, ICCD, ISPD, and DAC.