Hardware Design Methods for Bit-width Optimization
Seminars > Seminar Details
by Ray Cheung
Associate Professor
City University of Hong Kong
This talk aims to present the idea, motivations, challenges, applications of bit-width optimization, and its applications in approximate computing. A brief literature review and related research work at CityU Architecture Lab of Arithmetic and Security (CALAS) will be presented. In addition, ongoing research work with Oxford University by applying the Lagrange multiplier and automatic differentiation (AD) in automatically computing the precision of fixed-point variables, including improving area/time consumption, results of new case studies using High-Level Synthesis will also be presented in this talk.
Speaker Bio:
Dr. Ray C. C. Cheung received the BEng (Hons) and MPhil degrees in computer engineering and computer science & engineering from the Chinese University of Hong Kong (CUHK) and the DIC and PhD degrees in computing from Imperial College London (IC). He received the Hong Kong Croucher Foundation Fellowship and moved to Los Angeles, in Electrical Engineering department at UCLA. He is an Associate Professor in the Department of Electrical Engineering at the City University of Hong Kong and with the Digital Systems Laboratory. His current research interests include cryptographic hardware and processor architecture designs. He is the director of CityU Architecture Lab of Arithmetic and Security (CALAS) with 16 PhD graduates, the Treasurer of the IEEE HK Section, and the past chairman of IEEE HK Section CAS/COM Chapter.