FPGAs require a much longer compilation cycle than conventional computing platforms like CPUs.In this paper, we shorten the overall compilation time by co-optimizing the HLS compilation (C-to-RTL) and the back-end physical implementation (RTL-to-bitstream). We propose a split compilation approach based on the pipelining flexibility at the HLS level, which allows us to partition designs for parallel placement and routing. We outline a number of technical challenges and address them by breaking the conventional boundaries between different stages of the traditional FPGA tool flow and reorganizing them to achieve a fast end-to-end compilation.

The research produces RapidStream, a parallelized and physical-integrated compilation framework that takes in a latency-insensitive program in C/C++ and generates a fully placed and routed implementation. We present two approaches. The first approach (RapidStream 1.0) resolves inter-partition routing conflicts at the end when separate partitions are stitched together. When tested on the Xilinx U250 FPGA with a set of realistic HLS designs, RapidStream achieves a 5-7X reduction in compile time and up to 1.3X increase in frequency when compared to a commercial-off-the-shelf toolchain. In addition, we provide preliminary results using a customized open-source router to reduce the compile time up to an order of magnitude in cases with lower performance requirements. The second approach (RapidStream 2.0) prevents routing conflicts using virtual pins. Testing on Xilinx U280 FPGA, we observed a 5-7X compile time reduction and 1.3X frequency increase.

Speaker Bio:

Mr. Licheng Guo is a 5th-year Ph.D. advised by Prof. Jason Cong at the University of California Los Angeles. Licheng's research focus on co-optimizing HLS compilers (from C++ to RTL) and physical design tools (from RTL to hardware) to improve the circuit's maximal frequency and reduce the compilation time. Licheng has been awarded two Best Paper Awards in FPGA 2021 and FPGA 2022 for his research on frequency improvement and compile time reduction.

References

1. "AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs," FPGA'21.

2. "RapidStream: Parallel Physical Implementation of FPGA HLS Designs," FPGA'22.