In the past decade, CDSC has been exploring customizable computing, which emphasizes extensive use of customized accelerators on programmable fabrics for much greater performanc and energy efficiency. With Intel’s $17B acquistion of Altera in 2015 and Amazon’s introduction of FPGAs in its AWS public cloud in 2017, customizable computing is going from advanced research into mainstream computing.

Although the performance and energy efficiency benefits have been clearly demonstrated, a significant challenges, however, is the efficient design and implementation of various acceleration on FPGAs, which is a barrier to many software programmers. In this talk, I shall talk about our effort on developing an automated compilation flow from high-level programming languages to FPGAs. I start with a quick review of our early work on high-level synthesis. Then, I shall present our recent effort on source-code level transformation and optimization for customizable computing, including support of high-level domain-specific languages (DSL) for deep learning (with Caffe or TensorFlow), imaging processing (with Halide), and big-data processing (with Spark), and suppoort automated compilation to customized microarchictecture templates, such as systolic arrays, stencils, and CPP (composable parallel and pipelined).

Speaker Bio:

JASON CONG received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Distinguished Chancellor’s Professor at the Computer Science Department, also with joint appointment from the Electrical Engineering Department, of University of California, Los Angeles, the director of Center for Domain-Specific Computing (CDSC), and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. He served as the chair the UCLA Computer Science Department from 2005 to 2008. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and highly scalable algorithms. He has over 400 publications in these areas, including 11 best paper awards, three 10-Year Most Influential Paper Awards, and the first paper inducted to the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS after Xilinx’s acquisition). He was elected to an IEEE Fellow in 2000, ACM Fellow in 2008, and the National Academy of Engineering in 2017.