Research

We study about novel baseband processing architectures essential for 5G, 6G, and beyond. It addresses the extreme computational complexity and latency challenges posed by key technologies like massive MU-MIMO, intelligent reflecting surfaces (IRS) aided communication, etc. By pursuing a holistic algorithm-hardware co-design approach, we aim to develop highly efficient and low-latency solutions. This involves developing cost-efficient algorithm and realizing it into high-performance hardware, bridging the gap between advanced communication theory and practical hardware implementation.

We investigate efficient computing architectures designed to accelerate various intelligent systems. It includes building novel arithmetic operators, optimizing and compressing AI models, tackling the memory bandwidth bottleneck, and designing efficient accelerator architectures. The objective is to enable high-performance and low-power computing architecture on resource-constrained platforms. We also extend these intelligent computing principles to other complex domains, such as designing deep learning-based detectors for wireless signal processing. 

We research on designing flexible and scalable acceleration systems built upon the RISC-V core architecture. Leveraging the open and extensible nature of the RISC-V instruction set architecture (ISA), we develop domain-specific processors that merge the flexibility of software with the efficiency of dedicated hardware. We also design further optimized and extended core architecture with various architectural optimization techniques as well as in-depth exploration of vector extension, customized instruction, and priviledged instruction. This enables the creation of efficient, programmable, and high-performance accelerators targeting various computationally intensive applications.