CASYS

Takamaeda Lab. (Laboratory for Computer Architecture and Systems)

Department of Computer Science, Graduate School of Information Science and Technology, The University of Tokyo

CASYS is a laboratory for computer architecture (computer organization, processor architecture, design methodology, and ideal way of being computers). We are pursuing various research on highly efficient and trustworthy next-generation computing technologies, such as custom computing with FPGA and domain-specific hardware, algorithm/system co-design for machine learning, and high-level synthesis compilers for a productive hardware design environment. We are also pursuing software research on compilers, programming models, and frameworks for user/programmer-friendly computers.

We're looking for master's and Ph.D. students who are passionate about computer architecture and systems. Reach out if you're interested!

Research Interests

Computer Architecture
- Processor Architecture, Memory System
- Domain-Specific Architecture, FPGA system
- Secure Processor (TEE)
- Compute-in-Memory
- Computing with Emerging Devices
Hardware Design Technology
- High-Level Synthesis Compiler
- Algorithm/Hardware Co-design
Machine Learning System
- Distributed Machine Learning, Federated Learning
- LLM Inference/Serving System
- AI/LLM Chip

News

Our paper about a calibration technique for Processing-using-DRAM has been accepted by IEEE Computer Architecture Letters. The preprint is available here. (June 26, 2025)
Our poster paper about the design and implementation of secure memory systems using XLS high-level synthesis language (by Ozaki-san) will be presented at COOL Chips 2025. (March 28)
Prof. Takamaeda will provide an invited talk in Special Session "20 years of ARC: A Selection of Most Representative Papers" of ARC 2025 about Pyverilog, Python-based Hardware Design Processing Toolkit for Verilog HDL, presented in ARC 2015. (March 19, 2025)
Our paper about Rust-based domain-specific language for SFQ circuit design (by Oishi-san) has been accepted COOL Chips 2025. (March 18, 2025)
Our paper about an acceleration method of elliptic curve point additions on AMD Versal AI Engine (by Ohno-san) has been accepted COOL Chips 2025. (March 18, 2025)
Our paper about an acceleration method of 3D Gaussian splatting on AMD Versal AI Engine (by Shimamura-san) has been accepted COOL Chips 2025. (March 18, 2025)
Our position paper about Rust-based domain-specific language for SFQ circuit design (by Oishi-san) has been accepted 5th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE 2025). (February 17, 2025)
Our position paper about Hardware High-Level Synthesis with Linear Type System (by Tanaka-san, Kobayashi-lab) has been accepted 5th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE 2025). (February 17, 2025)
A new research grant project "Development of Universal TEE Architecture by Hardware/Software/Theory Cooperation" (Prof. Takamaeda as Co-PI) has been accepted by JST K Program. We pursue researches on secure processor architecture with memory encryption. (February 17., 2025)
Our paper about the memory access locality aware decision tree ensemble accelerator (by Tokuda-san) has been accepted by ACM Transactions on Reconfigurable Technology and Systems! This paper is accepted by the Journal Track of FPT 2024. (November 13, 2024)
Our papar about the pruning-based integer-only transfer learning method (by Anada-san) has been accepted by IEEE Embedded Systems Letters! (October 14, 2024)
Our paper about high-performance bitwise accumulation method using a commercial DRAM chip (by Kubo-san) has been accepted by NeurIPS 2024 Workshop Machine Learning with new Compute Paradigms (MLNCP 2024)! This is based on the joint research with Microsoft Research. (October 11, 2024)
Murakami-san has joined our laboratory as a Doctoral student. Welcome! (October 1, 2024)
Oishi-san and Ohno-san have joined our laboratory as Undergraduate students. Welcome! (October 1, 2024)
Our paper about a digital approximation architecture on Compute-in-Memory (with Prof. Yoshioka group) has been accepted by ICCAD 2024! (July 5, 2024)
Our paper about moment-propagation based variational inference method for Bayesian neural network (by Hirayama-san) has been accepted by IEEE TNNLS! (Febuary 14, 2024)

Old News

Our paper about a high-performance integrity verification mechanism for non-volatile memory systems has been accepted by IEEE Micro! (November 16, 2023)
Our paper about memory architecture obfuscation (by Tanaka-san) has been accepted by MCSoC 2023. (November 3, 2023)
Our paper about Bayesian neural network accelerator based on moment propagation (by Hirayama-san) has been accepted by MCSoC 2023. (November 3, 2023)
Our paper about delayed backdoor attack in federated learning (by Tsutsui-san) has been accepted by UbiSec 2023. (November 1, 2023)
Our paper about Analog/Digital CIM (by Yung-Chin Chen, Prof. Fujiki, and Prof. Yoshioka, Keio University) has been accepted by ASP-DAC 2024. (November 1, 2023)
Koike-san received IEEE CEDA AJJC Academic Research Award for his research on secure NVM architecture. (November 1, 2023)
Prof. Takamaeda serves as the Program Co-chair of FPT 2023 and the Guest Editor of ACM TRETS. (October 1, 2023)
Anada-san, Ozaki-san, Tokuda-san, and Nagatani-san have joined our laboratory as Undergraduate students. Welcome! (October 1, 2023)
Our paper about a high-level synthesis method for efficient memory systems (by Usui-san) has been accepted by ARC 2023. (June 30, 2023)
Prof. Takamaeda will have an invited talk at IEICE-CPSY workshop. (May 23, 2023)
Prof. Takamaeda received The Young Scientists’ Award, The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology, FY 2023! (April 7, 2023)
Project Assistant Professor Tatsuya Kaneko has joined our laboratory. Welcome! (April 1, 2023)
A new research grant project "Probabilistic Computing Platform based on Stochastic Thermodynamics" lead by Prof. Takamaeda has been accepted by KAKENHI KIBAN-A. We pursue researches on low-energy and reliable approximate computing technologies based on physics. (April 1., 2023)
Kuga-san, Koike-san, Hashimoto-san, Fujiwara-san (M2), and Fukami-san (B4) have graduated! (March 31, 2023)
Our paper about a high-performance integrity verification mechanism for non-volatile memory systems has been accepted by COOL Chips 26! (March 29, 2023)
Our paper about a hardware-friendly activation function for accurate binary neural networks (by Zhang-san) presented at CSA 2022 has received CSA Best Paper Award! (November 22, 2022)
Our paper about an FPGA-based acceleration method for video depth estimation (by Hashimoto-san) has been accepted by FPT 2022! (October 13, 2022)
Daichi Murakami (M2), Masayuki Usui, Keisuke Kamahori, Kotaro Shimamura, Sun Tanaka, Tasuku Fukami (B4), and Stefan Dangl (Internship) have joined our laboratory. Welcome! (October 3, 2022)
Our paper about a lottery-ticket based federated learning (by Tsutsui-san) has been accepted by CCNC 2023! (October 1, 2022)
Our paper about a hardware-friendly activation function for accurate binary neural networks (by Zhang-san) has been accepted by CSA 2022! (September 28, 2022)
Our paper about an efficient federated reinforcement learning method has been accepted by GLOBECOM 2022! (August 2022)
Koike-san won the IPSJ Computer Science Research Award for Young Scientists! (August 3, 2022)
Our paper about an acceleration method based on the microarchitectural support of approximate computing for decision tree ensemble (by Kamahori-san) has been accepted by HEART 2022! (May 11, 2022)
Akira Iga has joined our laboratory as a Master course student. Tatsuya Kubo, Kengo Suga, Masayoshi Tsutsui, and Sefutsu Ryu have become Master course students. Welcome! (April 1, 2022)
Tsutsui-san won the young excellent presentation award from IEICE-CPSY for his presentation about the communication reduction method for federated learning. (March 24, 2022)
Kubo-san won the young excellent presentation award from IEICE-CPSY for his presentation about the integrity verification scheme for non-volatile main memory. (March 24, 2022)
Hirayama-san will present his research activity on efficient Bayesian deep learning at SIG-FPAI. (March 2, 2022)
Kuga-san, Hashimoto-san, Kubo-san, Suga-san, Tsutsui-san, Ryu-san, and Kamahori-san will present their research activities at ETNET 2022. (February 23, 2022)
A WIP paper on the processor microarchitecture for approximate computing by Kamahori-san is accepted by YArch 2022! (February 23, 2022)
Hashimoto-san won the young excellent presentation award from IEICE-RECONF (Reconfigurable System) for his presentation about the FPGA-based acceleration method for Bilateral filter. (October 8, 2021)
Yinghao Ren (Master course student), Tatsuya Kubo, Kengo Suga, Masayoshi Tsutsui, and Sefutsu Ryu (Undergraduate student) have joined. Welcome! (October 4, 2021)
A new research grant project "D3-AI: Distributed AI for Dynamic and Diverse Environments" lead by Prof. Takamaeda has been accepted by JST CREST "Core technologies for trusted quality AI systems". We pursue researches on distributed machine learning and federated learning. (September 21, 2021)
Koike-san won the young excellent presentation award from IPSJ SIG-ARC (System Architecture) for his presentation about the fast and secure non-volatile memory mechanism. (August 3, 2021)
Our paper about the acceleration method for Bayesian neural networks by algorithm-hardware co-design is accepted by ASAP 2021 as a Full Paper! (June 3, 2021)
Out paper about the high-performance and lightweight FPGA implementation of Bilateral Filter is accepted by FPL 2021 as a Full Paper! (May 14, 2021)
Zhang-san has been accepted for Fellowship for Creation of Intelligent World. (April 30, 2021)
Koike-san, Hashimoto-san, and Fujiwara-san have become Master course students. Kuga-san (Master course student) have joined. Welcome! (April 1, 2021)
Hirayama-san has become a Ph.D student of The University of Tokyo. (April 1, 2021)
Ikeda-kun won the young excellent presentation award from IEICE SIG-DC (Dependable Computing) for his presentation about the DNN acceleration method based on the dead neuron prediction. (October 20, 2020)
Zhang-san (Ph.D. student), Koike-san, Hashimoto-san, and Fujiwara-san (Undergraduate student) have joined. Welcome! (September 24, 2020)
Ikebe-san (Technical Staff) has joined. Welcome! (September 1, 2020)
Our paper about an efficient hardware architecture for Bayesian neural network processing has been accepted for International Journal of Networking and Computing. (May 12, 2020)
Hirayama-kun won the excellent presentation award from JSAI for his presentation about variational Bayesian neural network at SIG-FPAI. (May 12, 2020)
Our paper about an FPGA-based acceleration method of random forest has been accepted for ARC 2020! (March 4, 2020)
NNgen (A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network) is available on GitHub. (December 6, 2019)
Secretary Yamaura-san has joined. (December 4, 2019)
Our paper about the annealing processor with Tokyo Tech, Hokkaido Univ., and Hitachi has been accepted for ISSCC 2020! (November 19, 2019)
CASYS Web page just opened! (October 8, 2019)
CASYS just started! (October 1, 2019）

Member

Faculty

Shinya Takamaeda-Yamazaki (Associate Professor, PI)

Staff

Fumiko Yamaura (Secretary)

Graduate Student (Ph.D. Course)

Shogo Yamazaki (D3)
Tatsuya Kubo (D2, BOOST NAIS)
Daichi Murakami (D1)
Masayuki Usui (D1, SPRING GX)
Sun Tanaka (D1, SPRING GX)

Graduate Student (Master Course)

Honoka Anada (M2)
Yoshiki Ozaki (M2)
Tomoya Nagatani (M2)
Daichi Tokuda (M1)
Mebuki Oishi (M1)
Ayumi Ohno (M1)
Hayato Kanazawa (M1)

Undergraduate

Exchange Program

Norbert Tremurici (TU Wien)

Alumni

Tatsuya Kaneko (March 2025, Project Assistant Professor)
Kotaro Shimamura (March 2023, Bachelor's Degree, March 2025, Master's Degree)
Yuki Hirayama (March 2021, Master's Degree, Hokkaido University, March 2024, Doctor of Computer Science, JSPS Research Fellow DC1)
Kohei Asano (March 2024, Master's Degree)
Akira Iga (March 2024, Master's Degree)
Kengo Suga (March 2022, Bachelor's Degree, March 2024, Master's Degree)
Masayoshi Tsutsui (March 2022, Bachelor's Degree, March 2024, Master's Degree)
Sefutsu Ryu (March 2022, Bachelor's Degree, March 2024, Master's Degree)
Peiqi Zhang (Semtember 2023, Leaving Doctoral course without Degree (Fellowship for Creation of Intelligent World))
Yinghao Ren (September 2023, Master's Degree)
Daichi Murakami (September 2023, Master's Degree)
Keisuke Kamahori (March 2023, Bachelor's Degree, June 2023, Leaving Master's course)
Kota Kuga (March 2023, Master's Degree)
Ryo Koike (March 2021, Bachelor's Degree, March 2023, Master's Degree)
Nobuho Hashimoto (March 2021, Bachelor's Degree, March 2023, Master's Degree)
Yoshiki Fujiwara (March 2021, Bachelor's Degree, March 2023, Master's Degree)
Tasuku Fukami (March 2023, Bachelor's Degree)
Stefan Dangl (March 2023, Internship, TU Wein)
Kazutoshi Hirose (March 2022, Ph.D., Tokyo Institute of Technology, and JSPS Research Fellow DC1)
Hikaru Ikebe (June 2021, Technical Staff)
Taiga Ikeda (March 2021, Master's Degree, Hokkaido University)
Kasho Yamamoto (March 2020, Ph.D., Hokkaido University, and JSPS Research Fellow DC2)
Yuka Oba (March 2020, Master's Degree, Hokkaido University)
Takumi Kudo (March 2020, Master's Degree, Hokkaido University)

Contact and Address

Address

4th floor, Faculty of Science Bldg. 7, The University of Tokyo,

7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

Room 401: Takamaeda's room
Room 402 and 403: Student room

Contact

Takamaeda: shinya_at_is_s_u-tokyo_ac_jp
Secretary: casys-secretary_at_is_s_u-tokyo_ac_jp

Replace _at_ and _ appropriately.

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