Resume
BABLU MUKHERJEE
bablu.iitm@gmail.com
+91-7810879542
https://scholar.google.com/citations?user=nGDnjbQAAAAJ&hl=en
Summary
Technically savvy and results-oriented professional with extensive experience in devising and strategic research for semiconductor device and process engineering. Hands-on experience of clean-room nanodevice fabrication, device processing, laboratory instrumentation & measurement techniques. Adept at exploring out-of-the-box and ground-breaking ideas for process and quality improvements. Excellent communication and interpersonal skills with ability to maintain robust relationships at corporate levels. Proficient in leading and training cross-functional teams to improve operational capabilities.
Professional with expertise in the field of 3D NAND memory as a semiconductor design rule engineer, specifically in NAND integration and memory technology development. Interest in contributing product improvements, new product introduction, cost reduction, speed increase and yield improvement in memory and storage company. I value collaboration, innovation, building competencies and excellence.
# Knowledge of advanced process technology nodes including design rules and layout verification flows for production as well as R&D designs.
# Failure Mode and Effects Analysis (FMEA) during design and provide new design solutions for designing for manufacturing (DFM) issues including Latch-up, ESD as well as process related failures (PFA, EFA) from PID, DE, CMP, DF.
# Project management of new technology node introduction for new memory design collaborating with process integration, OPC, design, scribe, yield analysis teams.
AREAS OF EXPERTISE
# Research & Development: Experimentalist with 10+ years experiences in Nanodevices & two-dimensional semiconductors & new device application developments. Subject definition, choice of study axis among known method; implementation of innovative technics, characterization to evaluate solution.
# Design Rule/Process Integration & Interface: Photomask/Reticle Integration; Layout & Design to help direct development efforts for a new 3D NAND generation from early development until manufacturing. Identify and address process issues & solve from layout design techniques.
# Process Improvement: Academic-Industry research & technology development. Development of plasma enhanced atomic layer etching (PEALE) & area-selective (PEALD) deposition processes for future nodes. Process integration & quality improvement of thin film for advanced memory and logic applications.
# Semiconductor Devices: Design and optimization of FETs, diodes, TFT, MOS devices. MOSFET device design, electrical characterization and device performance development. Reliability measures over number of cycles. Electrostatic device simulation
# Communication, Reporting & Documentation: Gathering different teams with their specific skills around various project, recognize the needs with characterization teams. Set out issues and dialogue on possible solutions. Reports, patents, publications & communication concerning project works.
# Leadership & Project Management: Task priority definition, multi-task & delay management. Project design, planning & execution, cutting-edge R&D project management. Lab management & safety lead, making decision, critical thinking & innovation strategy. Taught, trained & guided graduate students.
Experience
Senior Design Rule Engineer
Micron Technology August 2022 - Present
#Advanced NAND Technology Team: R&D NAND Design Rule/Process Integration Engineer
Team co-ordination:
# Co-ordinate the work of experienced engineers from Process Integration, Advanced Mask Design, Scribe & Frame, and Layout & Design to help direct development efforts for a new 3D NAND generation from early development until manufacturing ceases
# Pro-actively identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniques.
Project responsibilities:
# Assure that the right DRC’s (Design Rule Checks) are in place, assure appropriate reaction to deviation from established design rules
# Work with Yield Enhancement, Product Engineers, Defect analysis, Param, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design
# Help design and evaluate test structures to provide data for next generation devices, to quantify process margin on current devices
# Drive effective cross-functional communication on issue resolution, and support across node Design Rule alignment
# Maintain and enforce best possible communication between Process Integration, Product Engineering, Advanced Mask Design, Scribe & Frame, Layout & Design
Senior Process Engineer
ASM International N.V. Sep 2020 - August 2022 (2 years) #Corporate Research & Development Dept. (CRD)
# R&D at new process development group working on development of atomic layer etching & area-selective deposition processes in a single reactor. Characterization & in-situ analysis.
# Process development of plasma assist deposited films, gap-fill films for logic, GAA, flash memory, DRAM and MOSFET applications. Plasma cure, VUV cure and improvement of thin film properties.
# Gap-fill module development through hardware continuous improvement projects (CIPs). Repeatability, matching and tunability optimization using statistical methods (DOE).
Managerial aspects:
# Industry-Academia Collaboration
- Team lead of joint development projects (JDPs) with largest plasma science center
- Technology development support via process transfer & learning implementation
# Project initiation/management
- Manage cross-disciplinary projects on novel processes, personnel, schedules and plans
- Communicated with all organization levels in a global environment, addressing issues
JSPS Postdoctoral Fellow
National Institute for Materials Science
Nov 2017 - Aug 2020 (2 years 10 months)
# CMOS Technology Compatible Vertical p-Si/n-ReS2 Efficient Photodiode
# Floating-Gate (FG) Non-Volatile Memory (NVM) Devices Based on 2D TMDs Heterostructures
# Optical Driven Multi-level Flash Memory with high retention
Assistant Professor
Vellore Institute of Technology
May 2017 - Nov 2017 (7 months)
# Assistant Professor in Physics, School of Advanced Sciences. AGP 7,200. PB: 18,600 - 39,100
# Engineering Physics (PHY 1701) Course (Theory + Laboratory) for 3 batches undergraduates (60+)
# Academic duty apart from teaching: Research Award coordinator, Festivity coordinator
Postdoctoral Fellow
Indian Institute of Technology, Bombay
Sep 2015 - Apr 2017 (1 year 8 months)
# Few Layer ReS2 Plasmonic Phototransistor with High-Performance Optoelectronics
# Reversible hysteresis inversion in MoS2 field effect transistors
# Control of Two-dimensional Excitonic Light Emission via Periodic Structures and Applied Field
Postdoctoral Researcher
The George Washington University
Mar 2014 - Aug 2015 (1 year 6 months)
Plasmonic Gold Arrays on Monolayer MoS2 with Refractive Index Sensing
# Optical Properties and Extraction of Complex Electrical Permittivity of Monolayer MoS2
# Enhancing Optical Absorption and Scattering of Monolayer MoS2 with Plasmonic Au NPs
Research Assistant
National University of Singapore
Nov 2013 - Feb 2014 (4 months)
# Synthesis and Characterization of Atomically Thin Transition Metal Dichalcogenides Materials
# Au Nanoparticles Embedded on WSe2 Nanosheets on Sapphire as a Substrate for SERS Study
Research Internship
Leibniz Universität Hannover
May 2009 - Jul 2009 (3 months)
# Electrical Characterization of Si(1-x)Gex QDs Embedded into Crystalline Gd2O3 for Memory
# Sample Preparation using MBE and I-V, C-V Measurements of the MOS Devices
Education
National University of Singapore
Doctor of Philosophy (Ph. D), Physics of Nanodevices
2009 - 2013
Specialization: Experimental Nanoscience/optoelectronic devices.
Thesis title: Layered chalcogenides nanostructures: synthesis, characterization and optoelectrical applications.
# Optoelectronic Sensor of Individual Nanobelt with Different Surface Morphologies
# Laser Micropatterning of Nanostructures with Controlled Optoelectrical Properties for Sensors
Activities: 1D, 2D layer dry-transfer, Photolithography. Metal deposition with e-beam evaporator and sputtering process. FETs, diodes, MSM device fabrication using electron beam lithography (EBL). I-V, C-V, I-t, Pulse I-V electrical measurements.
Indian Institute of Technology, Madras
Master of Science (M.Sc.), Physics
2007 - 2009
Specialization: Material Science (Project), Advanced Electronics (special courses)
Thesis title: Synthesis, Structural, Optical and Electrical Properties Of Zinc Oxide nanoparticles
Activities: Electrical (I-V, C-V, hysteresis) & dielectric properties studied for thin film of ZnO nanoparticles.
University of Calcutta
Bachelor of Science (B.Sc.), Physics (Hons), Chemistry, Mathematics
2004 - 2007
Licenses, Certifications & Competence
Simulation & Designs Tool: FDTD, Lumerical Device, Design CAD, JMP 15.1, Python data analysis, Origin, design, layout and optimization of Memory/Logic devices, SPICE simulation
Analysis Tool: Ellipsometer, In-situ FTIR, XRD, XPS, Raman & PL, OES, Langmuir Probe, Plasma diagnostics, Matlab, Excel
Thin Film Fabrication Techniques: Lithography, Sputtering, PE-CVD, PE-ALD, PE-ALE, E-beam deposition, Cure, Properties improvement, Plasma treatment, VUV treatment
Statistical Methods - Engineering Statistics and Data Analysis - ASM
Intro to Python for Data Science Course - DataCamp - 6,451,890
Microsoft Excel - Excel from Beginner to Advanced - Udemy - UC-7G3WGSU1
Making academia–industry collaborations work - Elsevier
Badge on JMP User Community - SAS
Six Sigma White Belt Certification - Aveta Business Institute, Certification number: ImHOeaDmjz
Project Management - Harvard Business School
Skills
Semiconductor Device • NAND Flash Memory • Design Rule • Process Integration Engineering • Cross-functional Team Leadership • Nanotechnology • Process Engineering • Semiconductor Device • Design & Optimization • Layout design (Cadence Virtuoso, Calibre) • Plasma Processing • Project Management
Technical Achievements
PUBLICATIONS: JOURNAL PAPERS
1. Reaction Mechanism & Selectivity Control of Si-Compound ALE Based on Plasma Modification,
Langmuir (ACS) (I.F. 3.88), 37(43), 2021, 12663 –12672
R. Vervuurt,* Bablu Mukherjee,* K. Nakane, T. Tsutsumi, Masaru Hori, N. Kobayashi , *Equal first author.
2. ReS2/h-BN/Graphene Multifunctional Devices: Tunneling Diodes, FETs, Logic Gates & Memory,
Advanced Electronic Materials (I.F. 6.6), 7(1), 2000925(1-8), 2021,
Bablu Mukherjee*, R. Hayakawa, K. Watanabe, T. Taniguchi, S. Nakaharai, Y. Wakayama.
3. Laser Assist Multi-Level Nonvolatile Memory Few layer-ReS2/h-BN/Floating-gate Graphene,
Advanced Functional Materials (I.F. 16.8), 30 (42) 2001688, 2020,
Bablu Mukherjee*, A. Zulkefli, K. Watanabe, T. Taniguchi, Y. Wakayama, S. Nakaharai. (Citation: 59+),
Press Release: https://www.nims.go.jp/news/press/2020/08/202008250.html)
4. Enhanced Quantum Efficiency in Vertical Mixed-thickness n-ReS2/p-Si Heterojunction Photodiodes,
ACS Photonics (I.F. 6.88), 6 (9), 2277 - 2286, 2019,
Bablu Mukherjee*, A. Zulkefli, R. Hayakawa, Y. Wakayama, S. Nakaharai, (Citation: 30+)
5. NIR Schottky Photodetectors Based on Individual Single-Crystalline GeSe Nanosheet,
ACS Applied Materials & Interfaces (I.F. 8.75), 5 (19), 2013, 9594-9604,
Bablu Mukherjee, Y. Cai, H. R. Tan, Y. P. Feng, E. S. Tok, and C. H. Sow, (Citation: 234+)
6. Complex Electrical Permittivity of the Monolayer MoS2 in Near UV and Visible,
Optical Materials Express (I.F. 2.84), 5 (2), 2015, 447-455
Bablu Mukherjee, F. Tseng, D. Gunlycke, K. K. Amara, G. Eda, E. Simsek, (Citation: 132+)
*Corresponding author, h-Index: 17+, Citation: 1000+
# Raised major research funds. Research activities in
- 27 international peer-reviewed articles published.
- 10 international conference papers published
- 3 granted patents
- 24 Oral/poster presentations in international conferences
- 20 articles reviewed for international publishers including Nature, ACS, RSC, IOP & Springer
Complete List: https://orcid.org/0000-0002-5625-5948
PATENTS
1. ETCHING PROCESSES AND PROCESSING ASSEMBLIES (US 63/339,561)
Inventors: Bablu Mukherjee, Rene Henricus Jozef Vervuurt, Takayoshi Tsutsumi, Nobuyoshi Kobayashi, Masaru Hori.
2. METHODS FOR FILLING A GAP AND RELATED SYSTEMS AND DEVICES (US 17/530,983)
Inventors: Z. Liu, S. Kim, V. Pore, J. L. Yao, R. Borude, Bablu Mukherjee, R. H.J. Vervuurt, T. Tsutsumi, N. Kobayashi, Masaru Hori
3. METHODS AND ASSEMBLIES FOR DEPOSITING MATERIAL IN A GAP (ID: 63523935 ) US Patent 63/523,935
Inventors: Ranjit Borude, Bablu Mukherjee, R. Vervuurt, V. Pore, N. Kobayashi, T. Tsutsumi, Masaru Hori
SELECTED TALKS
1. Bablu Mukherjee, Replacement Gate NAND array development from design perspectives, Oral Presentation, October 24, 2023, Indian Technical Seminar, Micron Technology (ITS2023), India.
2. Bablu Mukherjee, Atomic Layer Etching of Ti-Compounds: Mechanism and Etch Selectivity Control for Advanced Device Fabrication, Online Presentation, September 28, 2022, International Conference on Solid State Devices and Materials (SSDM2022), Japan.
3. Bablu Mukherjee, Two-dimensional van der Waals heterostructures based electronic and optoelectronic device, Online Seminar, February 1, 2021, Chemistry and Physics Of Materials Unit (CPMU), Jawaharlal Nehru Centre For Advanced Scientific Research, India.
4. Bablu Mukherjee, 2D Materials and van-der-Waals-Heterostructure-based Optoelectronic Devices, International Virtual Conference (VCAN 2020) Invited Speaker, June 17, 2020, VIT University, India.
Link: https://www.youtube.com/watch?v=F7F2UkgJgLI
5. Bablu Mukherjee, 2D van-der-Waals Multilayer-ReS2/h-BN/Graphene Heterostructures Based Non-Volatile Memory Device for IoT Era, ICMAT 2019 Oral Presentation, June 23, 2019, Singapore.
AWARDS & ACHIEVEMENTS
# Ramanujan Fellowship 2022 from the Department of Science and Technology, Govt. of India.
# Research work highlighted in National Institute for Materials Science (NIMS) Press release.
# Excellent Poster Presentation Award in the MANA International Symposium 2019, Tsukuba, Japan.
# Nominated for Best Poster Award in the 79th JSAP Autumn Meeting 2018, Nagoya Japan.
# JSPS Fellowship 2017 – The Japan Society for the Promotion of Science, Japan.
# DAAD Scholarship 2009 – The German Academic Exchange Service - Germany.
# Award of Erasmus Mundus Scholarship (year 2009/2010) from University of Rennes 1-France.
# Ranked 57 in all India Joint Entrance Screening Test (JEST 2009) Examination.
# Qualified Graduate Aptitude Test in Engineering (GATE-2009) in Physics (Percentile: 93.17).
# Ranked top 3% among students appearing for JAM-2007 for admission at IIT.
# National top 1% in National Graduate Physics Examination NGPE 2006-07.