Welcome

Bablu Mukherjee, Ph.D.          

​Senior Engineer at Micron Technology - NAND Design Rule   

Dr. Mukherjee is a senior engineer at Micron Technology working with NAND Technology Integration team and Advanced NAND Technology team. His focus on Design Rule/Process Integration/Advance Layout interface. Prior to joining Micron, he has been working as senior process engineer in the corporate research and development department at ASM International holding a dual position with designated Assistant Professor at the Center for Low-temperature Plasma Sciences in Nagoya University. He received a Ph.D. degree (2013) in Physics from National University of Singapore, and a M.Sc. degree (2009) in Physics from the Indian Institute of Technology (IIT), Madras. He was a JSPS fellow (2017) at NIMS-Japan, Institute Post-doctoral fellow at IIT Bombay (2015), Post-doctoral Scientist at the George Washington University (2014), and DAAD fellow (2009) at Leibniz University of Hanover. Dr. Mukherjee has published 26 journal articles & 10 conference proceedings papers, given a total of 24 invited and regular presentations. He has experience in managing & executing various academic & industry collaboration projects. Mukherjee’s research is in experimental nanoscience and nanotechnology. His research interests include the development of process integration for semiconducting nanofabrication technology, the development of future generations smart devices, ultra-low-power electronic & optoelectronic devices, sensors, DRAM, NAND, Flash & storage devices.

AREAS OF EXPERTISE

# Design Rule/Process Integration & Interface: Photomask/Reticle Integration; Layout & Design to help direct development efforts for a new 3D NAND generation from early development until manufacturing. Identify and address process issues & solve from layout design techniques.

# Process Improvement: Academic-Industry oriented research & technology development. Development of plasma enhanced atomic layer etching (PEALE) & area-selective (PEALD) deposition processes for future technology nodes.

# Communication, Reporting & Documentation: Gathering different teams with their specific skills around various project, recognize the needs with characterization teams. Set out issues and dialogue on possible solutions. Reports, patents, publications & communication concerning project works.

# Leadership & Project Management: Experimentalist with 10+ years experiences in Nanodevices & two-dimensional semiconductors & new device application developments. Task priority definition, multi-task & delay management. Project design, planning & execution, cutting-edge R&D project management. Lab management & safety lead, making decision, critical thinking & innovation strategy. Taught, trained & guided graduate students.

EXPERIENCE

08/08/2022 – Present Micron Technology | Senior Engineer, Advanced NAND Technology (ANT)

 Technical aspects:

# NAND Design Rule/Process Integration Engineer.

# Top skills: Semiconductor Device • NAND Flash Memory • Design Rule • Process Integration Engineering • Cross-functional Team Leadership

NAND Design Responsibilities

• Responsible for NAND design rules and clean sheets.

• Worked closely with PI, photo, reticle, Design, and PE teams to define future technology nodes for all designs to reduce the number of reticles tapped out per design.

Reticle Creation and Verification

• Responsible for various steps involved in reticle creation for CMOS, Array, interconnect, and BEOL layers across NAND technology nodes in both R&D and Production.

• Involved in the definition, implementation, and verification of the CMOS and array.

Troubleshooting and Yield Improvement

• Heavily involved in troubleshooting various fab issues, especially layout-sensitive designs and yield loss-related design fixes.

• Created standalone DRCs to catch failing locations with the Design team and help increase yield with the YE team.

Simulation and Validation

• Responsible for requesting TCAD, structure, OPC, electrical, and Reliability simulations for Die database design edit requirements.

• Debugged test structure fail modes, including design rules validation and layout analysis to match specifications.

14/09/2020 – 31/07/2022 ASM International N.V. | Senior Process Engineer, CRD                                        

01/10/2020 – 31/07/2022 Nagoya University | Designated Assistant Professor, Center for Low-temperature Plasma Sciences

# This position is based in ASM’s Corporate R&D research group located at Nagoya University Japan. 

# Works with semiconductor processing equipment to research, develop and optimize plasma enhanced processes.

# R&D at new process development group working on development of atomic layer etching & area-selective deposition processes in a single reactor. Characterization, in-situ analysis, continuous improvement for future technology.

# Process development of plasma assist deposited films, gap-fill films for logic, flash memory, DRAM and MOSFET applications.

# Delivers creative solutions, creates inventions and develops intellectual property.

# University Collaboration (Managerial Aspects)

-    Joint development projects (JDPs) with largest plasma science center, team lead

-   Technology development support via process transfer & learning implementation

24/11/2017 – 11/09/2020 National Institute for Materials Science (NIMS) | JSPS Postdoctoral Fellow  

# CMOS Technology Compatible Vertical p-Si/n-ReS2 Efficient Photodiode

# Floating-Gate (FG) Non-Volatile Memory (NVM) Devices Based on 2D TMDs Heterostructures

# 2D Heterostructure based Multifunctional Devices: Tunneling Diodes, FETs, Logic Gates, & Memory

15/09/2015 – 30/04/2017 Indian Institute of Technology Bombay (IITB)| Institute Post-Doctoral Fellow

# Few Layer ReS2 Plasmonic Phototransistor with High-Performance Optoelectronics

# Reversible hysteresis inversion in MoS2 field effect transistors

# Control of Two-dimensional Excitonic Light Emission via Periodic Structures and Applied Field

03/03/2014 – 30/08/2015 George Washington University (GWU) | Post-Doctoral Scientist

# Plasmonic Gold Arrays on Monolayer MoS2 with Refractive Index Sensing

# Optical Properties and Extraction of Complex Electrical Permittivity of Monolayer MoS2

# Enhancing Optical Absorption and Scattering of Monolayer MoS2 with Plasmonic Au NPs

15/11/2013 – 14/02/2014 National University of Singapore (NUS) | Research Assistant

# Synthesis and Characterization of Atomically Thin Transition Metal Dichalcogenides Materials

# Au Nanoparticles Embedded on WSe2 Nanosheets on Sapphire as a Substrate for SERS Study

03/08/2009 – 30/07/2013 National University of Singapore (NUS) | Ph.D. Projects

# Nanobelts with Different Surface Morphologies for High-gain Photoconductivity

# Photocurrent Characteristics & Transport Mechanism of Individual Nanowire, Nanobelt devices

# Laser Micropatterning of Nanostructures with Controlled Optoelectrical Properties for Sensors

15/05/2009 – 24/07/2009 Leibniz Universität Hannover(LUH) | Internship Project

# Electrical Characterization of Si(1-x)Gex Quantum Dots Embedded into Crystalline Gd2O3 for Memory

# Sample Preparation using MBE and I-V, C-V Measurements of the MOS Devices

01/07/2008 – 01/05/2009                Indian Institute of Technology Madras (IITM) | Master Project

# Synthesis, Structural, Optical and Electrical Studies of ZnO Nanoparticles of different sizes

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