Notice

Our research paper collaborated with UCSD has been accepted to be presented at ESSERC 2025.

The title of the paper is “Integrated 64-Channel Spatiotemporally Patterned Multipolar Neural Stimulator with 150nA–10mA Current Range at 8V–20V Voltage Compliance,” which is a result of the collaboration with UCSD. During my sabbatical year from Aug 2022 to Jul 2023 at UCSD, Yongjae and I were involved in the research project developing a neural stimulator. After the sabbatical, Yongjae continued to discuss the team members at UCSD and contribute to the project. The first author is Jeonghoon Kim, PhD candidate at UCSD. Congratulations, Jeonghoon.

Dr. Yongjae Park's paper has been accepted for publication in IEEE Journal of Solid-State Circuits!

The title of the paper is “An Indirect ToF Sensor With In-Pixel Adaptive ΔΣ-Scheme for Background Light Rejection and Floating Diffusion Mismatch Cancellation,” which is one of Dr. Park's works during his PhD course. In this paper, we present a 160 × 120 indirect time-of-flight (iToF) sensor with an in-pixel adaptive ΔΣ-scheme that controls the number of sub-integration times adaptively to mitigate large background light (BGL) with alleviated reset noise penalty. A pixel-level charge amplifier is employed to suppress common-mode BGL charge, while the adaptive ΔΣ-scheme automatically selects the number of charge-subtraction operations with respect to BGL intensity to reduce the noise contribution from the charge amplifier. Additionally, an in-pixel floating diffusion (FD) swapping technique is proposed to alleviate non-idealities due to FD mismatches, such as depth linearity degradation and residual BGL charge. Congratulations, Dr. Park! 

Dr. Jee-Ho Park's paper has been accepted for publication in IEEE Journal of Solid-State Circuits!

The title of the paper is “A Compact Photocurrent Recording IC with High-Linearity Dual PWM Buffered R-DACs,” which is a part of Dr. Park's PhD work. In this paper, we introduce a photocurrent recording front-end, emphasizing both energy efficiency and compact size. The proposed front-end circuit comprises a voltage-controlled oscillator-based quantizer (VCOQ) and a digital low-pass filter for feedback current, optimizing conversion efficiency. Furthermore, a dual PWM-based buffered resistive digital-to-analog converter (R-DAC) is employed for enhanced linearity and area efficiency. The PWM logic, implemented with a digital counter instead of conventional structures, reduces dynamic power requirements. Additionally, integrating a coarse R-DAC with extended bit depth into the digital filter feedback loop significantly enhances dynamic range. The proposed architecture is further reinforced by loop gain calibration and a fast-settling feedforward path to mitigate parasitic effects on the passive integrator and reduce the data loss due to saturation caused by rapid input current fluctuations. Congratulations, Dr. Park! 

Welcome aboard to BIAS Lab.

Two students, Jungmin Oh and Junewoo Jeong joined our lab as MS candidates.

Welcome aboard to BIAS Lab! 

Jundong's paper has been accepted to be published in ISCAS!

The paper entitled “A Flash LiDAR with SA-Based Pulse Position Modulation for Multi-User Interference Cancellation” has been accepted to be presented at IEEE ISCAS, a flagship conference in the circuits and systems research field. This is the first report about the multi-user interference cancelation scheme for the successive-approximation histogramming TDC. Congratulations, Jun-Dong! 

Jubin's paper has been accepted to be published in ACS Nano!

 Contents: The paper entitled “Halide Perovskite Photodiode Integrated CMOS Imager” has been accepted to ACS Nano, one of the prestigious journals with an impact factor of 15.8. The paper introduces the world-first iToF sensor with a perovskite photodiode, showcasing the potential of beyond-Si materials for 2D and 3D imagers. This work results from the collaboration with UNIST, Imec, Postech, and Sogang University. Congratulations, Jubin! 

Dr. Bumjun Kim's paper has been accepted to be published in IEEE Journal of Solid-State Circuits!

The paper entitled “A CMOS Flash LiDAR Sensor With In-Pixel Zoom Histogramming Time-to-Digital Converters” has been accepted to IEEE JSSC, a flagship journal in the integrated circuits research field. This is the second generation of the flash LiDAR with in-pixel zoom histogramming TDC combining a coarse SA hTDC with a fine phase-domain TDC. Congratulations, Dr. Kim! 

Seonghyeok's paper is accpeted to be presented at ISSCC 2025

The paper entitled “An Asynchronous 160×90 Flash LiDAR Sensor with Dynamic Frame Rates of 5-250 fps Based on Pixelwise ToF Validation via Background Light Adaptive Threshold” is accepted to be presented at ISSCC 2025! In this paper, we present an asynchronous flash LiDAR sensor in that each pixel autonomously validates its own time-of-flight (ToF) value by comparing photon counts with a threshold estimated from background light (BGL) intensity, thereby dynamically adjusting its integration time to generate a reliable depth map. Rather than employing the complicated address event representation, only validated pixels are read out sequentially while other pixels continue to collect more photons. A bitwise arithmetic unit is devised to calculate the threshold, which can be accommodated in a compact pixel pitch. The prototype sensor fabricated in a 90-nm process achieves 6-cm precision and 8-cm accuracy over 1.5 to 22.5-m ranges indoors and a >95% true detection rate at 21 m under illuminations up to 30 klux. Additionally, it supports frame rates from 5 to 250 fps across various SNR conditions. Congratulations, Seonghyeok! 

Dr. Yongjae Park's paper is accpeted to be presented at ISSCC 2025

The paper entitled “A 4.6-µW 3.3-NEF Biopotential Amplifier with 133-VPP Common-mode Interference Tolerance and 102-dB Total Common-mode Rejection Ratio for Two-Electrode Recording System” is accepted to be presented at ISSCC 2025! In this paper, we present the AFE for two-electrode bio-potential recording systems featuring two key components: a CMI-Follower and a CM adaptive current-reuse OTA (CMA-CR-OTA). The proposed CMI-Follower provides an extremely low impedance by leveraging the Miller effect with a sensing capacitor, allowing the floating chip ground precisely to track the CMI and dynamically suppressing the CMI up to 133 VPP with a power consumption of 4.6 μW. Moreover, a noise-efficient CMA-CR-OTA is devised to enhance the system’s robustness against residual CMI caused by variations in parasitic capacitance between the chip ground and the earth ground, achieving a wide input CM range over 400-mVPP at a 1-V supply. Congratulations, Dr. Park! 

Dr. Su-Hyun Han's two papers have been accepted to be published in IEEE Journal of Solid-State Circuits!

 The titles of the two papers are “A 100×80 Flash LiDAR Sensor with In-Pixel Zoom-Histogramming TDC and Self-Referenced Single-Slope ADC Based on Analog Counters” and “A 3.1-µW Analog-Assisted Zoom Histogramming TDC in 35-µm Pixel Pitch for Flash LiDAR Sensor,” and both papers are extended versions of IEEE Symposium on VLSI Circuits and IEEE International Solid-State Circuits Conference held in 2022 and 2024, respectively. Congratulations Dr. Han! 

Our lab moved from UNIST to Sogang University after July 1.

Please contact us at Sogang University from now on. Thank you. 

Jung-Hye received the best paper on sensory systems runner-up award at ISCAS 2024!

Jung-Hye presented her paper entitled “An Indirect Time-of-Flight Sensor with Adaptive Multiple Sampling for High Depth Precision” at ISCAS 2024 held in Singapore. She received the best paper on sensory systems runner-up award as well as a 2024 IEEE CAS Student Travel Gran. Congratulations Jung-Hye! 

Welcome aboard to BIAS Lab.

Five students, Jae-Sung Lee, Do-Hyeon Lim, Jimin Ye, Yeongjin Mo, and Minsaeng Kang, joined our lab as MS candidates. Welcome aboard to BIAS Lab!