Hi! I'm a 3rd-year Ph.D. student at Georgia Tech under Dr. Muhannad Bakir. I'm currently working on system-level design and analysis for 2.5D integration. Especially, I'm specialized not only in designing chiplet and interposer layout of system architecture but also in analyzing Power, Performance, Area (PPA) and signal (SI), power (PI), thermal integrity using commercial EDA tools. Based on my skills, I've been involved in developing assembly design kit (ADK) for 2.5D/3D and chiplet/interposer co-design co-analysis methods to enhance PPA and SI and PI. 

I've been passionate about VLSI CAD since my undergrad. I worked as an undergrad research intern in VLSI CAD laboratory for 4 years. During this period, I participated in developing academia's first 3nm PDK and figured out methods to optimize block-level physical design for cutting-edge technology such as back-side power delivery network. I have experienced all levels of design from device to advanced packaging. I'm open to any collaboration. Please feel free to reach out!

See my publications here