Research
Research
Moving from die-centric packaging to application-specific system-level advanced packaging technology presents numerous reliability and qualification challenges. In 2.5D/3D packaging, while thermo-mechanical reliability challenges are recognized, it is crucial to address emerging package-specific electrical reliability issues, such as self-heating, moisture ingress, dielectric breakdown, ion-induced circuit instability, bond-wire corrosion, etc., with equal importance and integration into predictive design frameworks.
Microelectronic System Reliability (Ongoing)
Given the rapidly diversifying applications in robotics, self- driving cars, smart agriculture, edge computing, etc., ICs are being deployed in a variety of operating conditions and must be appropriately packaged for reliable operation in the extreme/ harsh conditions involving a time-varying combination of high humidity, high voltage, and high temperatures. For example, in the next generation of autonomous vehicles, a plethora of electrical systems and sensors are needed to be heterogeneously integrated to execute reliable sensing, rapid information processing, and accurate navigation regardless of the ambient circumstances. In this scenario, the true focus is on transitioning from Moore's law based die-centric packaging to application-specific system-level advanced packaging technology, termed the 'SysMoore era,' that ultimately results in enhanced Multiphysics chip package interactions (CPIs), new degradation/ failure modes, and the need for customized tools and methodologies for reliability testing. Indeed, this epochal transition in the packaged IC design offers an opportunity to rethink the traditional reliability tools, and methodologies and appropriately update them. Our research focuses on modeling, characterizing, and analyzing the reliability of electrical devices, packages, products, and the interactions between chips, packages, and boards.
Spoof Surface Plasmon Polariton Interconnect
The growing demand for high-fidelity, high-speed intra- and inter-chip communication for emerging applications like big data analysis and quantum information processing is leading us into an era where performance characteristics are expected to be dominated more by the interconnects than by the highly-scaled transistors and logic circuits. Though conventional optical interconnect technology offers bandwidth in the range of Gbps to Tbps, the overhead cost associated with electro-optical single conversion, modulation and coupling unfortunately poses hindrance to the application of this technology for short distance inter-chip communication. Spoof surface plasmon polariton (SSPP) interconnect, which is a new class of optical interconnect based on plasmonic quasi-particles capable of traveling along corrugated metallic surface at THz speed, has been drawing significant attention of the research community to design ultrafast chip-to-chip communication systems which can operate with minimal energy budget and maximal reliability. Though performance characteristics of standalone SSPP interconnects have recently been investigated in detail considering process variation, it remains to be seen how these characteristics will be affected by crosstalk resulting from electromagnetic interference between multiple SSPP communication channels operating in unison. In our research work, we explored how dimensional aspects such as groove heights, widths and numbers are going to influence crosstalk between SSPP channels operating at close proximity and provided a detailed analysis addressing these issues to further advance this emerging field of research for next generation high-speed chip-to-chip communication.
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Two-dimensional representation of the front-facing interconnects with the oscillation of coherent electromagnetic wave between the aggressor-victim channel pair in a 4-wire SSPP system.