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Very Large-Scale Integration (VLSI) Design Automation (DA) Lab at Yuan Ze University was established in August 2017 by Prof. Yu-Guang Chen. With 4 graduate students and 16 undergraduate students, we publish several conference papers and wom prizes in large competitions. The last student in VLSI-DA Lab will graduate at the end of 2021.
Very Large-Scale Integration (VLSI) Design Automation (DA) Lab at Yuan Ze University was established in August 2017 by Prof. Yu-Guang Chen. With 4 graduate students and 16 undergraduate students, we publish several conference papers and wom prizes in large competitions. The last student in VLSI-DA Lab will graduate at the end of 2021.
Prof. Yu-Guang Chen joined the Electronic Design Automation (EDA) Lab in August 2019. Currently we have 13 master students and more than 15 undergraduate students. The research topics include aging-aware design optimization and tolerance, Reliable In-Memory Computing (IMC) design, Power Distribution Network (PDN) Design and Optimization, Hardware accelerator for edge devices, and Hardware Security.
Prof. Yu-Guang Chen joined the Electronic Design Automation (EDA) Lab in August 2019. Currently we have 13 master students and more than 15 undergraduate students. The research topics include aging-aware design optimization and tolerance, Reliable In-Memory Computing (IMC) design, Power Distribution Network (PDN) Design and Optimization, Hardware accelerator for edge devices, and Hardware Security.
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