Wei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li, "An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing," accepted by IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Oct. 2021
Yu-Guang Chen, Ing-Chao Lin, Yong-Che Wei, "A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning," in Proc. of International Symposium on Quality Electronic Design (ISQED), Virtual Conference, Apr. 2021
Wen-Hsiang Chang, Li-Yi Lin, Yu-Guang Chen, and Mango Chia-Tso Chao, "Power Distribution Network Generation for Optimizing IR-Drop Aware Timing," in Proc. of IEEE/ACM International Conference On Computer Aided Design (ICCAD), Virtual Conference, Nov. 2020
Yu-Guang Chen, "An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling," in Proc. of IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), Taoyuan, Taiwan, Nov. 2020
Hao-Chun Chang, Li-An Huang, Kai-Chiang Wu, Yu-Guang Chen,"Selective Sensor Placement for Cos-Effective Online Aging Monitoring and Resilience," in Proc. of International Symposium on Physical Design (ISPD), pp.95-102, Virtual Conference, Mar. 2020
Yu-Guang Chen, Yu-Yi Lin, Ing-Chao Lin , "An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems. ", in Proc. of International Symposium on Quality Electronic Design (ISQED), pp.117-122, Virtual Conference, Mar. 2020
Yu-Guang Chen, Ing-Chao Lin, Jian-Ting Ke, "ROAD: Improving Reliability of Multi-core System via Asymmetric Aging," in Proc. of IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp.1-8, Westminster, CO, USA, Nov. 2019
Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu, "Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs," in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, FL, USA, July 2019
Kun-Wei Chiu, Yu-Guang Chen, Ing-Chao Lin, "An efficient NBTI-aware wake-up strategy for power-gated designs," in Proc. of Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, Mar. 2018
Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang, "Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach," in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 2017
Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang, "A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization," in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 2016
Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi, Shih-Chieh Chang, "Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation," in Proc. of International Symposium on Physical Design (ISPD), pp.41-48, Monterey, CA, USA, Mar. 2015 (Best Paper Nomination)
Yu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wen-Yu Wen, Yiyu Shi, and Shih-Chieh Chang, "Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs," in Proc. of IEEE/ACM Design Automation Conference (DAC), pp.1-6, San Francisco, CA, USA, June 2014 (Acceptance rate: 22.1%)
Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, and Shih-Chieh Chang, "Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits," in Proc. of Design, Automation & Test in Europe (DATE), pp.1-4, Dresden, Germany, March 2014 (Acceptance rate: 23.1%)
Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Geng Hui, and Shih-Chieh Chang, "Efficient Multiple-Bit Retention Register Assignment for Power Gated Design: Concept and Algorithms," in Proc. of IEEE/ACM International Conference on Computer-aided Design (ICCAD), pp.309-316, San Jose, CA, USA, Nov. 2012 (Acceptance rate: 24.3%)
Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu, and Shih-Chieh Chang, "Efficient On-line Module-level Wake-up Scheduling for High Performance Multi-module Designs," in Proc. of International Symposium on Physical Design (ISPD), pp.97-104, Napa Valley, CA, USA, March 2012 (Acceptance rate: 33%)
Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, and Shih-Chieh Chang, "NBTI-Aware Power Gating Design," in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp.609-614, Yokohama, Japan, Jan. 2011 (Acceptance rate: 34.4%)