PI: Prof. Yu-Guang Chen

Abstract

As CMOS technology continuous scaling down, a single chip can perform complicated data processing. Heterogeneous Multi-core System(HMS) can provide higher performance by appropriately performing task-to-core assignment. On the other hand, aging effect has become one of the most drastic challenges in modern IC design. Negative-Bias Temperature Instability (NBTI) effect can result in increased threshold voltage of pMOS transistors and may lead to timing failure after circuit aging. To mitigate or tolerance NBTI, previous researches developed different design structures as well as optimization strategies. However, only a few studies focus on NBTI-induced problems on HMSs. Therefore, in the proposal, we want to deeply study these NBTI-induced problems on HMSs, and develop a machine learning based algorithm to detect the aging situation of different modules in the HMSs, and propose a system level NBTI mitigation strategy. Specifically, this proposal addresses on the following two problems:
1.Using machine learning algorithm to deploy and calibrate aging sensors in different modules of HMSs.
2.NBTI-aware HMS system lifetime extension strategy
We will use machine learning algorithm to appropriately deploy aging sensors, and then develop a task-to-core mapping algorithm to extend the HMS system lifetime.

PI: Prof. Chien-Nan Liu

Co-PI: Prof. Yu-Guang Chen

Abstract

While the computing power of computers are increased a lot, the applications of artificial intelligence (AI) have become the research focus in recent years. DARPA’s ERI (Electronics Resurgence Initiative) project also puts a large budget on Intelligent Design of Electronic Assets (IDEA), which targets on the combination of EDA and AI to generate the required designs and layouts without human in the loop. Therefore, several top EDA research teams collaborate on this project to study the AI applications on advanced EDA techniques. It should be able to make specific breakthroughs on related issues and lay a solid foundation for the EDA techniques in Taiwan. In this project, 5 different topics are included as follows.
Sub-Project 1: Design Automation Techniques for Hardware Implementation of Artificial Neural Networks
Sub-Project 2: AI-Assisted Design Automation and Verification Techniques for Heterogeneous Systems
Sub-Project 3: Machine Learning Based NBTI Detection and Mitigation for Heterogeneous Multi-Core Systems
Sub-Project 4: Intelligent Routing and Standard Cell Synthesis using Machine Learning and Deep Learning
Sub-Project 5: Machine and Deep Learning Based Digital/Analog Circuit Sizing and Layout Synthesis

PI: Prof. Chun-Yao Wang

Co-PI: Prof. Yu-Guang Chen

Abstract

To de-centralize the service from AI server, we need to solve the key issue of high volume computation and high power demand in the AI applications. Edge computing paradigm is a possible solution to this issue, which use edge devices to collect and process input data for de-centralization. Since edge devices usually have limited resources and are battery constrained, reducing computation and power consumption is quite important. Also, error tolerance or accuracy recovery in the edge devices also have to take into account. Thus, in this project, we are going to study the architecture, and algorithms for AI edge computation considering performance and power optimization.

Sub-Project I: Approximate Computing and Optimization for Binarized Neural Network: Applying BNN to the edge devices on mobile platforms can elevate the energy efficiency and reduce model size. In the model inference, we use approximate computing and optimization techniques to reduce the operation count and hardware resource requirement under the accuracy constraint.

Sub-Project II: Efficient Adaptive Neural Network for AI Chip Considering Aggressive Performance Optimization: This project will consider two types of errors: 1. Errors caused by aggressive timing or power optimization 2. Errors caused by variations in Computation-In-Memory (CIM). This project will analyze the relationship between computation errors and power consumption. Meanwhile, propose an efficient adaptive NN that maintains the accuracy of it while meeting power optimization.

Sub-Project III: Design, Automation and Methodology for Energy-efficient Edge AI Computation based on Quantized Neural Networks: We propose to, based on layer-wise quantization, explicitly address DNN’s energy efficiency problem from the software, hardware, and integration perspectives

PI: Prof. Chun-Yao Wang

Co-PI: Prof. Yu-Guang Chen

Abstract

The goal of this project is to organize the CAD Contest at ICCAD 2021

PI: Prof. Yu-Guang Chen

Abstract

The goal of this project is to develop PBL-based teaching material about Supply-Chain Level Security Protection Design for Chip and Hardware.