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Digital Logic Design
DLD Outline
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Number System
Boolean Algebra
Karnaugh Map
TebularMethod
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SR Latch Working
Sequential Analysis
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CCP CPU
Digital Logic Design Lab
1 Lab Equipment
2 Logic Gates
3 Universal Gate Logic
3 Boolean Function
4 DeMUX n Decoder
5 Binary Adder
6 ROM from DRL
7 SR Latch
8 Design with D-FF
9 JK FF
10 Shift Registers
11 Counters
12 Decade Counter
13 Install HDL
14 VHDL Intro
15 VHDL MUX
Lab Report Guidelines
Data Science Lab
Python basics
Classes and objects
Tuples and lists
Pandas and dataframes
Data Statistics
Webscraping using BFS
Frequency Analysis
Regression model
Naive Baysian
kNN and Decision Tree
SQL Database
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Spring 2025 office hours are Mondays from 11:45 to 3:00PM and Fridays from 11:45 to 1.00 p.m. Please email or request specific times using the form below.
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