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Digital Logic Design Lab
1 Lab Equipment
2 Logic Gates
3 Universal Gates
4 Encoders n Decoders
5 Binary Adder
6 ROM from DRL
7 Design with D-FF
8 Shift Registers
9 Counters
10 GHDL n GTKWave
11 VHDL MUX
Universal Gate Logic
VHDL Intro
SR Latch
JK FF
Lab Report Guidelines
Decade Counter
Digital Logic Design
DLD Outline
Presentations
Number System
Boolean Algebra
Karnaugh Map
TebularMethod
Past Exams
SR Latch Working
Sequential Analysis
Sequential Design
CCP CPU
Complaints
Data Science Lab
Python basics
Classes and objects
Tuples and lists
Pandas and dataframes
Data Statistics
Webscraping using BFS
Frequency Analysis
Regression model
Naive Baysian
SQL Database
kNN and Decision Tree
Office hours
Good Deeds
Sec B
Sec A
5 Binary Adder
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