Table of Contents:

Ferroelectric Devices

Ferroelectric devices based on doped hafnium oxide (HfO₂) have been reported as promising candidates for low-power logic, nonvolatile memory (NVM), and in-memory computing applications due to their compatibility with CMOS technology and low-power operation. They have several advantages over other types of electronic devices, including high endurance, low power consumption, and fast switching speeds. 

NCFET has been reported to overcome the fundamental limit of conventional CMOS technology (60 mV/dec). It can be used in low-power circuit applications due to the internal voltage amplification provided by the ferroelectric layer. Additionally, it can offer a higher ON current and a lower threshold voltage compared to conventional FETs.

We have studied the device physics, design, and compact modeling of these devices to enable the design of next-generation electronics using Si-FeFET and FE-HEMT devices for storage applications and NC-CFET for logic applications. Our research on ferroelectric devices results in the following publications: 

• A. Kumar, D. Pyngrope, and A. Dasgupta, “A SPICE-Compatible Compact Model for Ferroelectric-Gated GaN-HEMTs,” 2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2026, pp. 1-3.

• A. Kumar, A. Saxena, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Compact Modeling of Flicker and Thermal Noise in Ferroelectric Devices,” International Compact Modeling Conference (ICMC), San Francisco, CA, USA, 2025.

• A. Kumar, S. Mehrotra, A. Bulusu, and A. Dasgupta, “A Method to Generate Additional Volatile States Using Single-domain Ferroelectric Field-Effect Transistor,” in Journal of Applied Physics, vol. 137, no. 13, 134101, Mar. 2025.

• A. Kumar, S. Mehrotra, A. Bulusu, and A. Dasgupta, “Performance Projection of Gate-All-Around (GAA)-based Negative Capacitance Complementary FET (NC-CFET) Relative to Standard CFET,” in IEEE Journal of the Electron Devices Society, vol. 13, pp. 814, 2024.

• A. Kumar, A. Bulusu, and A. Dasgupta, “Performance Projection of Negative Capacitance Complementary FET (NC-CFET): Device-Circuit Co-design,” 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

• A. Kumar, N. Mishra, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Impact of Doped Hafnium Oxides on Memory Window and Low-Frequency Noise in Ferroelectric FETs,” in IEEE Transactions on Electron Devices, vol. 71, no. 7, pp. 4015–4020, July 2024.

• A. Kumar, M. Ehteshamuddin, A. D. Gaidhane, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Universal Compact Model of Flicker Noise in Ferroelectric Logic and Memory Transistors,” in IEEE Transactions on Electron Devices, vol. 71, no. 1, pp. 18–22, Jan. 2024.

• A. Kumar, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Landau-Based Compact Model for Multi-Domain Ferroelectric Field-Effect Transistors,” International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2023.

• A. Kumar, G. Pahwa, A. K. Behera, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs,” 2022 IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1–5.

ULTRARAM

ULTRARAM is a non-classical charge-trapping-based emerging NVM that exhibits fast, non-volatile, high endurance (>10^7 P/E cycles), long retention (>1000 years), and ultra-low switching energy per unit area characteristics. It breaks the paradigm of the unachievable universal memory idea. Unlike a single SiO2 barrier in a flash, the novelty lies in the InAs/AlSb triple-barrier resonant tunneling (TBRT) mechanism. The TBRT structure provides a high-energy electron barrier with no bias, allowing fast resonant tunneling at program/erase pulses (±2.5V) with a switching energy approximately ten times smaller than that of Flash. However, ULTRARAM is in its early stages of development and needs to overcome several challenges.

We have developed the first physics-based compact model of ULTRARAM that captures charge trapping and detrapping in the floating-gate (FG) using TBRT physics, which is used to calculate device characteristics. This model can be used for circuit design with a ULTRARAM memory device. We have also analyzed the performance matrix of ULTRARAM cells as an artificial synapse for in-memory computing applications. Our research on ULTRARAM results in the following publications: 

• A. Kumar, P. D. Hodgson, M. Hayne, and A. Dasgupta, "Artificial Synapse based on ULTRARAM Memory Device for Neuromorphic Applications", in Journal of Applied Physics, vol. 139, no. 12, Mar. 2026.

• A. Kumar, P. D. Hodgson, J. Ashforth-Pook, M. Hayne, and A. Dasgupta, "ULTRARAM: An Emerging Memory Technology for NVM and Low-Power Neuromorphic Systems", 2026 27th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2026, pp. 1-7.

• A. Kumar, M. Dar, P. Hodgson, D. Lane, P. Carrington, E. Delli, R. Beanland, S. Mehrotra, M. Hayne, and A. Dasgupta, "Physics, Modeling, and Benchmarking of ULTRARAM: A Compound Semiconductor-based Memory Device” in Journal of Applied Physics, vol. 138, no. 9, 095702, Jul. 2025.

• A. Kumar, M. Ehteshamuddin, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Physics-based Compact Model for ULTRARAM Memory Device,” 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

• A. Kumar and A. Dasgupta, “Compact Modeling of Compound Semiconductor Memory ULTRARAM: A Universal Memory Device,” 2024 Device Research Conference (DRC), College Park, MD, USA, 2024, pp. 1-2.

News covered by:

• Semiconductor Today (link)

• Compound Semiconductor Magazine (link)

• Storage Newsletter (link)

• Acrofan (link)

ML for EDA

Machine learning (ML) is revolutionizing Electronic Design Automation (EDA) by improving efficiency, accuracy, and scalability in the design and optimization of electronic systems. Both foundries and design companies rely on EDA to support their businesses. A key component in EDA that bridges the foundry technology and IC design is device compact models. ML models, such as neural networks and reinforcement learning, reduce simulation overhead, automate repetitive tasks, and provide predictive insights into design metrics. Additionally, ML-assisted algorithms can be used to optimize advanced node semiconductor devices. There are many ways to optimize two or more target objectives. On the one hand, we have TCAD-based optimization, a trial-and-error method that requires experience and a deep understanding of device physics. In contrast, the other method is a framework that utilizes an ML-assisted genetic algorithm to maximize or minimize the value of target objectives.

We have been working with various ML-based models for semiconductor device optimization and NN-augmented compact modeling. Our research on ML-based modeling and optimization results in the following publications: 

• A. Singh, M. Ehteshamuddin, A. Kumar, M. Shukla, D. Pyngrope, S. Parandiyal, K. Sheelvardhan, A. K. Behera, S. Ray, A. Somani, S. Roy, and A. Dasgupta, "Complete Charge-Based Artificial Neural Network Augmented Compact Model for Common Multi-Gate FETs” in IEEE Transactions on Electron Devices, vol. 73, no. 5, pp. 2593-2599, Mar. 2026.

• M. Ehteshamuddin, K. Sheelvardhan, A. Kumar, S. Guglani, S. Roy, and A. Dasgupta, “Machine Learning-Assisted Multiobjective Optimization of Sub-2nm Node Gate-All-Around Transistor for Logic and RF Applications,” in IEEE Transactions on Electron Devices, vol. 71, no. 2, pp. 976–982, Feb. 2024.

• M. Ehteshamuddin, A. Kumar, S. Roy, and A. Dasgupta, “Optimizing Memory Window and Polarization of a Fe-CAP Using Machine Learning Assisted Genetic Algorithm Framework,” International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2023.