Publications

--------------------- Patent Filed ---------------------

1. A. Kumar and A. Dasgupta, “Ferroelectric Field Effect Transistor and Method to Perform the Multi-Bit Operation Using the Ferroelectric Field Effect Transistor,” May 2024, Indian Patent Application No. 202411038573.

--------------------- Journals ---------------------

1. M. Shukla, A. Kumar, and A. Dasgupta, “Novel Charge Partitioning Compact Model including Field Dependent Mobility Degradation Effect for Nanoscale MOSFETs,” in IEEE Transactions on Electron Devices, Dec. 2025.

2. S. Sarker, A. Kumar, and A. Dasgupta, “Physics-Based Compact Model of Subband Energy for GAAFETs including corner rounding and Geometric Variability Analysis Utilizing Monte Carlo Simulation,” in Solid State Electronics, Vol. 230, 109253, 2025.

3. A. Kumar, M. Dar, P. Hodgson, D. Lane, P. Carrington, E. Delli, R. Beanland, S. Mehrotra, M. Hayne, and A. Dasgupta, "Physics, Modeling, and Benchmarking of ULTRARAM: A Compound Semiconductor-based Memory Device” in Journal of Applied Physics, vol. 138, no. 9, 095702, Jul. 2025.

4. M. Dar, Gagan, K. Sheelvardhan, A. Kumar, T. Pramanik, S. Salahuddin, C. Hu, and A. Dasgupta, “A Compact Model for Perpendicular STT-MRAM Incorporating Free and Pinned Layer Thickness Dependence, Accurate Bias Dependence and Real-Time 3D Switching Dynamics,” in IEEE Transactions on Electron Devices, vol. 72, no. 8, pp. 4123-4130, Jun. 2025. 

5. S. Parandiyal, A. Kumar, M. Ehteshamuddin, A. Singh, K. Sheelvardhan, S. Ray, A. Somani, S. Roy, and A. Dasgupta, "Metalearning-Based Adaptive Compact Modeling Framework for Advanced Transistors across Technology Nodes,” in IEEE Transactions on Artificial Intelligence, vol. 6, no. 10, pp. 2810-2818, Mar. 2025.

6. A. Kumar, S. Mehrotra, A. Bulusu, and A. Dasgupta, "A Method to Generate Additional Volatile States Using Single-domain Ferroelectric Field-Effect Transistor,” in Journal of Applied Physics, vol. 137, no. 13, 134101, Mar. 2025.

7. A. Kumar, S. Mehrotra, A. Bulusu, and A. Dasgupta, “Performance Projection of Gate-All-Around (GAA)-based Negative Capacitance Complementary FET (NC-CFET) Relative to Standard CFET,” in IEEE Journal of the Electron Devices Society, vol. 13, pp. 814-821, 2025.

8. N. Mishra, A. Kumar, A. Dasgupta, and S. Roy, “Study of Enhanced Ferromagnetic Behavior of Mn-doped 2D Janus Cr2S2I2 Monolayer,” in IEEE Journal of the Electron Devices Society, vol. 13, pp. 876-882, 2025.

9. A. Kumar, N. Mishra, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Impact of Doped Hafnium Oxides on Memory Window and Low-Frequency Noise in Ferroelectric FETs,” in IEEE Transactions on Electron Devices, vol. 71, no. 7, pp. 4015–4020, July 2024.

10. M. Ehteshamuddin, K. Sheelvardhan, A. Kumar, S. Guglani, S. Roy, and A. Dasgupta, “Machine Learning-Assisted Multiobjective Optimization of Sub-2nm Node Gate-All-Around Transistor for Logic and RF Applications,” in IEEE Transactions on Electron Devices, vol. 71, no. 2, pp. 976–982, Feb. 2024.

11. A. Kumar, M. Ehteshamuddin, A. D. Gaidhane, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Universal Compact Model of Flicker Noise in Ferroelectric Logic and Memory Transistors,” in IEEE Transactions on Electron Devices, vol. 71, no. 1, pp. 18–22, Jan. 2024.

12. S. Sarker, A. Kumar, M. Ehteshamuddin, and A. Dasgupta, “Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes,” in IEEE Journal of the Electron Devices Society, vol. 11, pp. 510–517, 2023.

--------------------- Conferences ---------------------

1. A. Kumar, D. Pyngrope, and A. Dasgupta, “A SPICE-Compatible Compact Model for Ferroelectric-Gated GaN-HEMTs,” 2026 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2026, pp. 1-3.

2. A. Kumar A. Saxena, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Compact Modeling of Flicker and Thermal Noise in Ferroelectric Devices,” 2025 International Compact Modeling Conference (ICMC), San Francisco, CA, USA, Jun. 2025.

3. A. Kumar and A. Dasgupta, “Compact Modeling of Compound Semiconductor Memory ULTRARAM: A Universal Memory Device,” 2024 Device Research Conference (DRC), College Park, MD, USA, 2024, pp. 1-2.

4. A. K. Behera, N. Chauhan, A. Kumar, T. Rampal, S. De, A. Dasgupta, S. Dasgupta, and A. Bulusu, “Assessing the Performance of Ferroelectric Junctionless FET for NVM,” 2024 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Athens, Greece, May 2024.

5. A. Kumar, M. Ehteshamuddin, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Physics-based Compact Model for ULTRARAM Memory Device,” 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

6. A. Kumar, A. Bulusu, and A. Dasgupta, “Performance Projection of Negative Capacitance Complementary FET (NC-CFET): Device-Circuit Co-design,” 2024 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

7. S. Sarker, A. Garg, P. Ranjan, A. Kumar, and A. Dasgupta, “Physics-Based Core Compact Model of 2D MoS2 FET Considering Fermi-Dirac Statistics,” 2024 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

8. K. Sheelvardhan, S. Parandiyal, M. Ehteshamuddin, A. Kumar, S. Roy, and A. Dasgupta, “Neural Network augmented Physics-based Hybrid Compact Model for Computational Efficiency Improvement,” 2024 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

9. A. Kumar, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Landau-Based Compact Model for Multi-Domain Ferroelectric Field Effect Transistors,” International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2023.

10. M. Ehteshamuddin, A. Kumar, S. Roy, and A. Dasgupta, “Optimizing Memory Window and Polarization of a Fe-CAP Using Machine Learning Assisted Genetic Algorithm Framework,” International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2023.

11. M. Shukla, M. Ehteshamuddin, A. Kumar, K. Sheelvardhan, and A. Dasgupta, “Novel Charge Partitioning Compact Model including Field-Dependent Mobility Degradation Effect for Nanoscale MOSFETs,” International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2023.

12. A. Kumar, G. Pahwa, A. K. Behera, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs,” 2022 IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1–5.

13. S. Manikandan, N. Chauhan, N. Bagga, A. Kumar, S. Banchhor, S. Roy, A. Bulusu, A. Dasgupta, and S. Dasgupta, “Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors,” 2022 IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1-4.

--------------------- Invited Talks ---------------------

1. A. Kumar, “Ferroelectric devices for advanced memory technologies,” IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.

2. A. Kumar, “Compact modeling of emerging memory devices,” IEEE EDS Workshop on Devices and Circuits (WDC), Goa, India, Jan. 2025.