Syllabus

Course Syllabus

Introduction

Design

• The Development Life Cycle
  • Requirements
  • Specifications
  • Functional View
  • Architecture
• Making it Work
  • Design - A Graphical View
  • Components and Signals
  • Refining the Design
    • Data Path and Control

HDL and Modeling

• Traditional Approach
• HDL Based Design
• Models, Modeling, and Snythesis
• Modeling and Verilog HDL

Verilog HDL

• Basic Concepts
• Verilog Models
  • Gate Level
  • Data Flow
  • Behavioural
• Tools and Techniques
• Testing and Verifying the Design
• System Tasks and Functions
• Synthesizing the Design

Data Path Components

• Selection - Multiplexing
• Routing - Demultiplexing
• Encoding - Decoding
• Arithmetic Devices
• ALU - Comparison
• Storage Elements
  • Registers
  • Latches
  • Finite State Machines and State Assignments
• Memories

Signal Processing on FPGAs

• Designing & Implementing FIR Filters
• Implementing FFT on FPGA
• Modulation & Demodulation

Communication

• Coding
• Protocols

Signal Integrity and the Real World

• Time and Timing
• Combinational Logic
  • Verilog Delay Models
• Latches and Flip-Flops
  • Verilog Models
  • Boundary Conditions
  • Signal Skew
• Clocks and Clock Distribution
  • Design a Clock System
• Working with the Real World
  • Parasitic Devices
  • Digital Signaling and Signal Quality
  • Timing Analysis and Worst Case Design
  • Performance Optimization
  • Power & Energy

Testing

• The Test Process
• Vocabulary
• Motivation
• Documentation
• Test Case Design
• Contemporary Test Problems and Techniques
  • Scan Design
  • Boundary Scan and JTAG
  • Design for Test