In this year's offering of the course, you will be able to choose one of two tracks: in the "Existing Labs" track you will perform the 5 labs that have been used in recent offerings of 371. In the "Future Labs" track, you will start by doing the same first 3 labs as in the "Existing Labs" track, and then you will work on creating your own labs that potentially could be used by future students. The Future Labs track requires you to take more initiative to define, structure, and execute the project. The Future Labs track is potentially more risky (since your project might not work), could end up taking more time, but may lead to your learning more. In the Existing Labs track it is more clear what you need to do. Another difference is that in the Future Labs track, the TAs will not be able to provide as much help, because you will be trying to do something that they have not previously done. In terms of content, the Existing Labs track puts more emphasis on using the Nios soft processor (a processor that you configure the FPGA to implement). In the Existing Labs track, you will spend more time working with the Qsys software for configuring and programming the Nios. In the Future Labs track, you will be putting more effort into creating your own Verilog designs.
Digital Design Principles and Practices, 4th edition, John F. Wakerly, Prentice Hall, 2006 - Primary Text
You must demo each project to your TA or instructor. Prior to demonstration, please have ready a one page design document as described below. You will not be able to demo the lab until this document is completed and looked over by your TA. For the demos each team member must be prepared to answer questions pertaining to the project development, functionality of the project, and each members individual contribution. Demos will take place during the assigned lab sections.
Dates when the labs will be available and when they are due are posted on the Labs page of the class website.
Late lab reports will receive a minus 20% per day late. No project will be accepted after one week.
The final report will be due at the time of the final demo.
The final report will be due at the time of the final demo.
Labs 1-3 - 40%
Lab 4 / Project Proposal & Preliminary Results - 10%
Lab 5 / Final Project - 45%
Participation - 5%
Laboratories are scheduled in the EEB 137 electronics laboratory. Every student should gain experience with the physical performance of a lab: building circuits, taking measurements, etc. Labs should be done as a group, with all members of the group present. Group roles should rotate - circuit assembler, meter reader, results analysis. Each group should submit one lab report.
Point distribution will vary with the assignment, and each weekly project must include signed statement of individual contribution
If you have a documented disability and wish to discuss academic accommodations, please contact me as soon as possible. I am happy to make every reasonable accommodations.
You are free to work with others in interpreting assignments and on developing facility with the software and hardware tools we will be using. However, the lab assignments must be completed solely with your own team and exams are expected to be done individually
On the lab projects, you will work in groups of no more than two persons. Please include one page in each write up explaining the exact role that each person played in the design and execution of the solution. This sheet should be signed by both members.
The literature is full of a great variety of very good and efficient algorithms. Taking advantage of these is common practice. However, for any such code you use, you must cite the source…you will be given a failing mark on the lab if you do not cite your sources in your listing - this is not something to be hand written in after the fact, it must be included in your source code… This is an easy step that you should get in the habit of doing…
Please note very carefully, this does not include your fellow class mates code.
Cheating is a very serious offense. If caught cheating, your case will be referred to College of Engineering for investigation and discipline. Don't cheat.
To avoid creating situations where copying can arise, you should not e-mail or post your design files. You can post general questions about interpretation and tool use but limit your comments to these categories. If in doubt about what might constitute cheating, just don't or send the professor email describing the situation.