5/31/19: Final Lab Reports and Extra Credit Final Demos
All final lab reports, regardless of section, are due June 6th at 11:59pm to canvas with a video showing the work you did. We will not be accepting late submissions for this so turn in on time.
Extra credit final demos will be help Thursday June 7th, at 11:00 am, in Gates Commons (CSE 691). Make sure to signup here and include any equipment that you might need. We will provide a projector with a vga and hdmi input.
Presentations will be 2 slides maximum + demo and will take only 3 minutes (including the demo) per group.
5/10/18: In addition to your project proposals, please prepare a quad chart as outlined in lecture today.
You will need to add it to the slide deck as you will be presenting it to the class. Here is an outline.
5/10/18: Dropbox for lab 3 extra credit on canvas
Even if you did it as a group, please submit your own copy to canvas.
5/3/18: If you have any questions about what constitutes a good final project, feel free to email the TAs in your section or Professor Smith and ask.
Looking ahead to the week of May 7th, we are working on the project proposals and project prototypes. They are due the week of May 14th, so you have a full lab section before it's due to ask questions and get help. Beware of project scope as you won't want to over scope your project. We want to aim for a project that can be completed in 3 weeks.
Project proposal template and lab 4/5 specification documentation have been posted in the labs tab. The project proposal template will be updated very soon with an exact point total.
5/1/18: For Lab 3 we are revising the demo late day policy so that you can demo any number of days late and still get 80% of the total points.
5/1/18: Added Qsys Screenshot to Resources Tab
4/30/18: DE1-SoC SystemCD added to Resources page
This CD includes wide variety of design examples that you can copy and use as starting points for your own projects, each with their own Quartus project and documentation. Also includes the System Builder, a handy GUI tool that lets you pick the pins/peripherals you'd like to use and automatically creates a blank Quartus project with pin definitions and a top-level Verilog module.
4/24/18: Lab 3 Spec Updated with RAM details
4/24/18: Lab 3 is live and Lab 2 Survey
Hello All, as lab 2 demos wrap up this week there are two things to be addressed that are due at the same time.
1. A survey will become available to students after completion of lab section this week on canvas. Please fill this out for participation points.
2. Lab 3 spec is live. Lab 3 builds on lab 2 stuff and has multiple smaller tasks to complete so pay attention to the deliverables section.
4/18/18: Lab 2 Arrival and Departure Diagram in FAQ section
4/17/18: Lab 2 Clarifications and Updates
We are currently updating the lab spec for better wording and clarifying certain point. Please look at the lab 2 spec so you have the most up to date information.
4/16/18: Lab 2 Documents
Lab 2 Demo Rubric has been added to the LABS tab and the new Lab Report Template, used for lab 2 and on, is available there too.
4/3/18: Lab 1 Schematic Design
For the 4th counter in lab 1, please use Quartus' schematic design tool. A tutorial for the design tool can be found in the "Resources Tab" under "Helpful Links".
Part of lab 1 is verifying that the physical system on the FPGA works as designed. Please provide either a correct LED output or showing your TA the Signal Tap waveform when demoing. You are free to choose.
3/28/18: Lab 1 Clarification
Using iverilog and gtkwave in lab 1 is optional. You can also choose to use quartus and modelsim. Coding lab 1 in verilog vs systemverilog is also optional. You can choose. You will still be required to provide counter output waveforms in your lab report regardless if you choose to use gtkwave or modelsim.
3/28/18: Lecture slides from yesterday are posted
3/26/18: Welcome to the CSE / EE 371 Home Page!
Please go to lab section this first week! Happy first day of class.
An intermediate level course in the design and development of digital /embedded systems. The course is intended to build on the concepts introduced and developed in EE 271 or CSE 369. The main objective of the class is to provide students with a theoretical background to and practical experience with the tools, techniques, and methods for solving challenges related to modeling complex systems using the Verilog hardware description language (HDL), signal integrity, managing power consumption in digital systems, and ensuring robust intra and inter system communication working with systems of mid-level complexity.
To learn the formal design cycle for specifying, designing, implementing, testing, and optimizing FPGA based digital systems. As our target hardware platform we will work with the Altera DE1-SOC development board, which includes the Cyclone V FPGA and a variety of peripheral devices . The hardware side of the applications will be specified then designed, modeled, and tested using the Verilog HDL and the libraries and tools provided under the Quartus II Prime development environment. We will synthesize then download the tested modules onto the DE1-SoC board where they will be integrated into a complete working system.