EE477 - s18 lab2

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2

LATCH and FLIP-FLOP DESIGN and SPECTRE Simulations

worth 12% of Final Grade

Due April 3, 2018, 5:00 PM

V_dd = 1.8 v.

RULES FOR LATCH AND FLIP-FLOP:

For the schematic and layout simulations follow these rules:

Rule 1: Attach your inverter#1 as a "load" to the flip-flop output. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell.

Rule 2: The clock and all input signals should have a rise and fall time of .05 ns.

Rule 3: The clock should have a 50% duty cycle.

Rule 4: Proper functioning of a flip flop includes having the low output be less than or equal to .1 V_dd and the high output being greater than or equal to .9 V_dd.

Rule 5: The inputs to the flip flops are: clock, /clock, Data (D), synchronous reset, synchronous Load and synchronous /Load. The output to the flipflops is Q.

Rule 6: The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop multiplexer).

Rule 7: The transistors in the gates used in the flip-flop should be sized as they were sized for Lab 1b.

Rule 8: Do not use ratioed (pseudoNMOS) logic. Do not use dynamic logic or dynamic storage (not covered yet).

Rule 9: Well and substrate ohmic contacts (ntap and ptap) required for all your layouts:

* Every cell should have a well and substrate contact.

* For larger cells, include at least two ohmic contacts (ntap and ptap) per 50x50 lambda square, one for the p-substrate and the other for the n-well, assuming there are both NMOS and PMOS transistors in the space.

* Every separate block of n-well should have at least one ohmic contact.

* For all your contacts, you will get the best design if you use multiple minimum-size contacts for large contact areas and not large contacts. Cadence will do this automatically for you if you try to use large contacts.

1. LATCH AND FLIP-FLOP SCHEMATIC DESIGN/SIMULATION

A. DESIGN a SCHEMATIC for a positive edge-triggered D flip flop.

Use only the cells you have already constructed to design a latch, and use two latches to build a CMOS D flip-flop schematic in Cadence. Make sure the last inverter in the second latch that outputs Q is the #2 inverter. That way you can drive several gates from the flip flop.

Design the two latches as separate cells and then place them together to form the flip-flop. You can use one of the larger inverters in additional places in the flip flop if it gives you a faster design without using significantly more area.

Design Requirements:

Assume the flip-flop is clocked and can be synchronously reset. Reset can be active low or high, depending on your design.
clock, /clock, Data D, synchronous reset, Load and /Load are inputs to your design.
Load is active high.
When Load is low, the data will recirculate, regardless of the clock.
The flip-flop should be positive edge-triggered.

B. SCHEMATIC SIMULATIONS for the flip-flop you built in Cadence using SPECTRE

1) Be sure to try all possible combinations of data inputs versus present state of the flip flop, including the waveforms shown below. Note: This is a functionality test: you can do it with a slow clock frequency.

2) Be sure you test reset. Start with clock low, D high and Load high and then raise clock. This entire time, you should assert reset and show when reset is enabled, the output does not follow Data D instead it goes to 0.0v. Then un-assert reset and show that D propagates to the output.

3) Adjust the timing of your clock to be as fast as possible and still have your flip flop work properly. You could use the waveform below to perform this test but you should check that when data changes from high to low or low to high, the output can be produced before the next clock falls. Also make sure the inputs have settled a setup time before the rising edge of the clock. You should have output data stable before the clock falls and the first latch should complete latching any new data before the clock rises. We consider the data to be changed when it has risen to 90% of final value (Vdd) or fallen to 10% of original value (Vdd). To find a starting point for this test, you could find the setup time, and the clock-to-Q delay (including the propagation delay in the second latch back to the mux) as your initial clock period to start your testing.

4) Measure the setup time. The setup time is the amount of time before the rising edge of the clock that input D must be stable (the time difference between the 50% of the Data D voltage range and the 50% of the clock voltage range).

Note: The waveforms shown below show the order of changes of inputs between clock, data and load you are to use for the functional test simulations.

2. LATCH AND FLIP-FLOP LAYOUT DESIGN/SIMULATION

A. LAY OUT the flip-flop:

Use the same layout methodology you used in Lab #1, using only the bottom three layers of metal, metal 1, metal 2 and metal 3.

Suggestion: At this point if you have routing problems you may need to adjust the layout routing or cells slightly. If you do adjust your cells, describe it in your report.

B. SIMULATE THE LAYOUT for the flip-flop you built in Cadence using SPECTRE

For the layout simulations, again, be sure to follow all rules.

1) Repeat the same simulations you performed for the schematic.

2) Record the delay between V_in (D) changing and the propagation time in the second latch back to the mux. Use the definitions of delay given in the text as the time between the input achieving 50% of its final value and the output achieving 50% of its final value. This will give us the sum of the setup and clock-to-Q times, with setup the time before the clock, and clock-to-Q the time after the clock. Note the required clock period with 50% duty cycle.

Note: You should measure two values, one for the output falling transition and another for the output rising transition.

For this part, the clock frequency should be maximum that will give correct output, and the data transition should complete a setup time before clock rises. An easy way to perform this measurement is by focusing in on one clock falling edge transition and set the input stable for a setup time, then measure the delay.

The setup time is the amount of time before the rising edge of the clock that input D must be stable (the time difference between the 50% of the Data D voltage range and 50% of the clock voltage range).

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. You will have one chance to upload your files. All files and report should be in a single Tar or zip file, uploaded to D2L. Failure to follow these instructions could result in deduction of points.

LAB Hint: Do not name files or cells starting with a number - like 4inputnand. Cadence and/or SPECTRE might have trouble with this. They might also have trouble with names like /clk, so use notclk instead.

What to turn in:

Your Lab 2(in pdf format) should contain the following items:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number (5%).
A description of the flip-flop you built, including a transistor-level or gate-level circuit diagram printed from Cadence (15%).
A description of all the schematic simulation experiments you ran with SPECTRE (5%).
Submit all the waveforms for the flip-flop schematic. Show waveforms for all the simulation experiments including the measurements of the reported values in item 5 below. Put your input and output waveforms onto multiple graphs so we can read them more easily (20%).
Report the values for schematic: clock maximum speed, setup time. (5%)
The latches and flip-flop layout screen captures. Make sure to show the pin names (20%).
A description of all the layout simulation experiments you ran with SPECTRE (5%).
Submit all the waveforms for the flip-flop layout. Show waveforms for all the simulation experiments including the measurements of the reported values in item 9 below. Put your input and output waveforms onto multiple graphs so we can read them more easily (20%).
Report the values for layout: clock maximum speed, setup time, and the delay between V_in changing and V_out(Q) changing (5%).

Items 1-9 should all be in a single report. Tar this report along with the SPECTRE netlists for the schematic and the layout of your final D-flip flop - this should not appear in the report, but be submitted as a separate file, tarred with the report, and uploaded to the D2L. Also include the si.out files, renamed so we know what each one represents.

Do not put the SPECTRE netlists into the report itself.

Note: We only need the netlist files, si.out files and no other files.

Netlist files can be obtained in the ADE L (simulator window) go to simulation--> netlist--> display