EE477 - s18 hw5

Homework Assignment #5

E477 Spring 2018 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 4/6/18

OR Ecopies due 5 PM 4/6/18 using the "Assignment" Function on DEN

This assignment is worth 150 points

Assume lambda is .1 microns. Assume Vdd is 1.8 V, V_tp0 is -.4 V. and V_tn0 is .4 V. V_tpbodyeffect is -.55 V. and V_tnbodyeffect is .55 V.

Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns.

You can use these values for transistor ks (betas): ß_n (k_n) (beta)= 219.4 W/L _ A(microamps)/V² and ß_p (k_p)(beta)= 51.9 W/L m A/V² .

e₀ (epsilon) = 8.85 X 10 ^-14 F/cm, e_oxide(epsilon) = 3.9, and e_silicon(epsilon) = 11.7.

N_A=4X10¹⁸cm^-3 (substrate doping)

N_D=2X10²⁰ cm^-3 (source/drain doping)

N_A(sw)=8X10¹⁹ cm^-3 (Sidewall (p+) doping)

n_i²= 2.1X10²⁰ cm^-3 (intrinsic carrier concentration of silicon)

x_j (diffusion depth) =32 nm

KT/q= .026 V (thermal voltage)

Cjbsn = 17.27 x 10-4 pF/ _m² and Cjbswn = 4.17 x 10-4 pF/ _m (micrometer).

Cjbsp = 18.8 x 10-4 pF/ _m²and Cjbswp = 3.17 x 10-4 pF/ _m (micrometer).

Assume drain capacitances are the same as the source (in practice they are not).

1. (10%) Compute the worst-case rising and falling RC time constants at point A of the circuit below using the Elmore delay method. Assume all transistors are unit sized and wire capacitance is lumped. Assume Rchn = 1100 ohms. Cg(n+p) = 20 ff, Cd(n+p) = 20ff, and Cint = 10 ff, except Cint0 = 5 ff. Rint for interconnect1 is 10 ohms, interconnect2 is 5 ohms, and interconnect3 is 8 ohms.

2. (20%) Is CBADEFGHIBACAGD an Euler path for the NMOS transistors shown in the circuit below. If so, mark it. If not, find the longest path you can starting with the suggested Euler path. Show a stick diagram of the NMOS transistors in the Euler path (or longest path).

3. (10%) Assume you have the following wires to place in a layout. The numbers give starting and ending x positions of the wires. Place them using the Left Edge algorithm. For this example, two wires in the same track can start and end at the same point. So a wire can end at 4 and another can start at 4.

3,7 4,6 1,5 2,5 5,7 3,8 1,6 5,8 7,8 6,7

4. (10%) Compute the gate capacitance for a PMOS transistor in the saturation region. The PMOS transistor dimensions are: W=10 lambda, L= 4 lambda. Assume L_D=0.1 nm.

5. (13%) Use the fringing field figure on p. 274 of the text (in Lecture 19 notes). Assume the FFF is 20. Approximate the w/l ratio if t/h = 0.4. What does this indicate about the ratio between wire width and oxide thickness?

6. (9%) Assume electrons in a wire on a CMOS chip move at 0.24meters/sec. Assuming wire length is 10 microns, what electron rise/fall time would never require us to consider inductance?

7. (8%) In a large chip, clock signals can arrive 10ps early and 90ps late. Explain what timing of the flip flop is affected by the clock skew and how it is affected. t_hold is the hold time, t_setup is the setup time, t_q is the clock-to-Q time, and t_period is clock period.

8. (10%) Compute the Cdp for the source diffusion sidewalls that do not face the channel of a unit size NMOS transistor with diffusion 4 lambda x 6 lambda. Use the diffusion capacitances given above.

9. (5%) Calculate the resistance of a wire .09 cm long and 6 lambda wide that has resistance .08 ohms/square.

10. (5%) If a signal has rise time of 99ps, what are the values of the signal at 0ps and 99ps?

11. (7%) How far does the poly have to extend beyond the gate area (gate extension rule)?

12) (8%) What design rule for metal layers helps prevent electromigration (metal migration)?

The material required for problems 13 and 14 will be covered in Lectures 20, 21 or 22.

13. (25%) Use Elmore delays to find the longest path in the network of gates shown below to A<B out, assuming all transistors are unit size, and all inputs arrive at the same time. Assume Cgnunit=Cgpunit=Cdnunit=Cdpunit, and there are no wire delays.

14. (10%) If a metal interconnect has capacitance 10ff, resistance 10 ohms, and drives a single inverter with total gate capacitance 20ff, if Rchp of the driving inverter is 100 ohms, and the diffusion capacitance of the driving inverter is 20ff, would doubling the width of the wire make the circuit faster? Use a lumped RC model for the wire.