University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2b

Latch/FF Layout and SPECTRE Simulations

Due April 6, 2017, 5:00 PM


Vdd = 1.8 v.

Well and substrate contacts (ntap and ptap) required for all your layouts : Make sure your ohmic contacts meet the following requirement:

* Every cell should have a well and substrate contact.


* For larger cells, include at least two ohmic contacts (ntap and ptap) per 50x50 lambda square, one for the p-substrate and the other for the n-well, assuming there are both NMOS and PMOS transistors in the space.


* Every separate block of n-well should have at least one ohmic contact.

* For all your contacts, you will get the best design if you use multiple minimum-size contacts for large contact areas and not large contacts. Cadence will do this automatically for you if you try to use large contacts.

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LATCH and FLIP-FLOP DESIGN

********************************************* NOTES FOR FLIP-FLOP ***********************************

For the layout simulations follow the following notes:

Note 1: Attach your inverter#1 as a "load" to the flip-flop output. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell.

Note 2: The clock and all input signals should have a rise and fall time of .05 ns.

Note 3: The clock should have a 50% duty cycle.

Note 4: Proper functioning of a flip flop includes having the low output be less than .1 Vdd and the high output being greater than .9 Vdd.

Note 5: The inputs to the flip flops are: clock, /clock, Data D, synchronous set, synchronous Load and synchronous /Load.

Note 6: The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop).

Note 7: The transistors in the gates used in the flip-flop should be sized as they were sized for Lab 2a.

Note 8: Do not use ratioed (pseudoNMOS) logic. Do not use dynamic logic or dynamic storage (not covered yet).

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A. LAY OUT the flip-flop:

Use the same layout methodology you used in Lab #1, using only the bottom three layers of metal, metal 1, metal 2 and metal 3.

Suggestion: At this point if you have routing problems you may need to adjust the layout routing slightly. If you do adjust your cells, describe it in your report.

B. SIMULATE THE LAYOUT for the flip-flop you built in Cadence using SPECTRE

For the layout simulations, be sure to follow notes 1-8

1) Repeat the same simulations you performed for the schematic in Lab 2a.

2) Note the delay between Vin (D) changing and Vout (Q) changing. This is not exactly the clock period because we are ignoring the propagation time in the second latch back to the mux. Use the definitions of delay given in the text as the time between the input achieving 50% of its final value and the output achieving 50% of its final value. This will give us the sum of the setup and clock-to-Q times, with setup the time before the clock, and clock-to-Q the time after the clock.

Note: You should measure two values, one for the output falling transition and another for the output rising transition.

For this part, the clock frequency should be maximum, the data transition should complete a setup time before clock falls. An easy way to perform this measurement is by focusing in one clock falling edge transition and set the input stable for a setup time, then measure the delay Vin to Vout.

The waveform shown in lab2a may not test both inputs/outputs transitions, so you may need additional input combinations for this measurement.

3) Measure the setup time off the same waveform you measured the delay in part 2 of this lab. The setup time is the amount of time before the falling edge of the clock that input D must be stable (the time difference between the 50% of the Data D voltage range and 50% of the clock voltage range).


********************************************SUBMISSION**************************************************************

What to turn in:

Your Lab 2b (in pdf format) should contain the following items:

  1. A cover sheet (title page) giving your name, date you submitted the lab, title, and student number (5%).
  2. The latches and flip-flop layout screen captures. Make sure to show the pin names (25%).
  3. A description of all the simulation experiments you ran with SPECTRE (10%).
  4. Submit all the waveforms for the flip-flop layout. Show waveforms for all the simulation experiments including the measurements of the reported values in item 5. Put your input and output waveforms onto multiple graphs so we can read them more easily (50%).
  5. Report the values for layout: clock maximum speed, setup time, and the delay between Vin changing and Vout(Q) changing (10%).


Items 1-5 should all be in a single report. Tar this report along with the SPECTRE netlists - these should not appear in the report, but be submitted as separate files, tarred with the report, and upload to the D2L.


Do not put the SPECTRE netlists into the report itself.


Note: We only need the netlist files for the layout of your final D-flip flop.


Netlist files can be obtained in the ADE L (simulator window) go to simulation--> netlist--> display


IMPORTANT: Once you upload there will be no deletions or reuploads allowed. You will have two chances to upload your files. All layouts must be in color except with permission of the instructors. Failure to follow these instructions could result in deduction of points.


LAB Hint: Do not name files or cells starting with a number - like 4inputnand. Cadence and/or SPECTRE might have trouble with this. They might also have trouble with names like /clk, so use notclk instead.


Notes from former TA Yilda Irrizarry-Valle:


1) Running layout simulations is the same as running schematic simulations (same steps, see the last page of Cadence Tutorial). The tutorial is on DEN-->Course Documents-->Cadence Tools.


2) A few things are different:


a. You should open the ADE L simulator window from the extracted view, not from the layout view (see the last page of Cadence tutorial).


b. In stimulus input part you will need to setup the ground signal to 0 (dc voltage).


c. To plot the signals, you do it in the same way as for the schematic. The only difference is that you need to choose the signal (the metal or poly line) in the extracted view.