University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2a Revised

Latch/FF Design, Layout and SPECTRE Simulations

Due March 28 30, 2017, 5:00 PM

V_dd = 1.8 v.

LATCH and FLIP-FLOP DESIGN

********************************************* NOTES FOR LATCH AND FLIP-FLOP ***********************************

For the schematic and layout simulations follow the following notes:

Note 1: Attach your inverter#1 as a "load" to the flip-flop output. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell.

Note 2: The clock and all input signals should have a rise and fall time of .05 ns.

Note 3: The clock should have a 50% duty cycle.

Note 4: Proper functioning of a flip flop includes having the low output be less than .1 V_dd and the high output being greater than .9 V_dd.

Note 5: The inputs to the flip flops are: clock, /clock, Data D, synchronous set, synchronous Load and synchronous /Load.

Note 6: The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop).

Note 7: The transistors in the gates used in the flip-flop should be sized as they were sized for Lab 1.

Note 8: Do not use ratioed (pseudoNMOS) logic. Do not use dynamic logic or dynamic storage (not covered yet).

************************************************LATCH AND FLIP-FLOP SCHEMATIC DESIGN/SIMULATION**********************************

A. DESIGN a SCHEMATIC for a negative edge-triggered D flip flop:

Use only the cells you have already constructed to design a latch, and use two latches to build a CMOS D flip-flop schematic in Cadence. Make sure the last inverter in the second latch that outputs Q is the #2 inverter. That way you can drive several gates from the flip flop.

Design the two latches as separate cells and then place them together to form the flip-flop. You can use one of the larger inverters in additional places in the flip flop if it gives you a faster design.

Rules:

• Assume the flip-flop is clocked and can be synchronously set. Set can be active low or high, depending on your design.
• clock, /clock, Data D, synchronous set, synchronous Load and synchronous /Load are inputs to your design.
• Load is active high.
• When Load is low, the data will recirculate, regardless of the clock.
• The flip-flop should be negative edge triggered.

B. SCHEMATIC SIMULATIONS for the flip-flop you built in Cadence using SPECTRE

1) Be sure to try all possible combinations of data inputs versus present state of the flip flop, including the waveforms shown below. Note: This is a functionality test: you can do it with a slow clock frequency.

2) Be sure you test set. Start with clock high, D low and Load high and then lower clock. During this time you should assert set and show when set is enabled, the output does not follow Data D instead it goes to 1.8 V.

3) Adjust the timing of your clock to be as fast as possible and still have your flip flop work properly. You could use the waveform below to perform this test but you should note that we need to also make sure that when data changes from high to low, the output can be produced before the next clock falls. Note: Make sure the inputs have settled a setup time before the falling edge of the clock. You do not need to have data stable before the clock rises but the first latch should complete latching any new data before the clock falls. We consider the data to be changed when it has risen to 90% of final value (Vdd) or fallen to 10% of original value (Vdd). To find a starting point for this test, you could find the setup time, the clock-to-Q delay and the propagation delay in the second latch back to the mux as your clock period.

4) Measure the setup time. The setup time is the amount of time before the falling edge of the clock that input D must be stable (the time difference between the 50% of the Data D voltage range and the 50% of the clock voltage range).

Note: The waveforms shown below show the order of changes of inputs between clock, data and load you are to use for the simulations.