University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #1b

Logic Gate Layout and Simulation Experiments

Due Mar. 21, 5:00 PM Via the DEN Online Assignment Function (100 points, worth 4% of final grade)

YOU MUST WORK INDEPENDENTLY ON THE LABS: THERE ARE NO PROJECT GROUPS

3. LAYOUT: (35%) Layout the cells you designed in Lab 1a with Cadence (each circuit layout is a "cell"). Use the TSMC technology (NCSU_TechLib_tsmc02) as instructed in lab. Put at least one ntap and ptap (ohmic contacts) in each cell. If you have multiple n-wells in a cell, each needs an ohmic contact.

Required Layout Design Methodology:

Design all of your cell layouts so that they can be placed next to each other either vertically or horizontally without having layers connect that should not.

Use a uniform methodology to design all the gates, and only use metal 1 and metal 2 for interconnect.

Make sure that you minimize the use of poly and only use poly around the gate region of each transistor.

Your goal is to insure that it is easy to build more complex designs out of your gates, and to keep the cells small, with few layer changes for each connection.

Extend your methodology to design compound gates as well.

Keep in mind as you design the inverters that you may want to alter the design later with wider transistors, so consider how you can do that without changing your layout methodology.

At this point in the semester, try to minimize the white space to create cells that are as small as possible, but easily combined into larger circuits. One hint: you could design the cells so that the output of each cell lines up exactly with an input of every cell type. The output and input can line up horizontally or vertically.

The following is one example of such a methodology:

"Design each cell to be the same height. Power and ground will be routed horizontally later, and the input to each cell could be vertical. The output should come out horizontally on the metal 2 layer. You might want to a style similar to the cells discussed in class."

This is only an example. Instead, you might choose to design each cell to be the same width, for example. You might route the inputs to the cell horizontally, and use different layer assignments than the example.

You can put contacts for inputs and outputs somewhere inside that they can later be accessed when you connect cells to each other. The contacts do not need to be necessarily inside, that would depend on the methodology you choose to use.

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4. (10%) VERIFICATION: Use LVS to verify that your cell layouts are identical to the schematics. Note: When doing the LVS you do not need to have the load inverter. The load inverter is only used for simulation purposes and it is not part of your cell design.

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Cell Layout SPECTRE Simulations 35%

A. Simulate the cell layouts you designed using SPECTRE (inverters, NANDs, transmission gate and compound gate) with added ntaps and ptaps.

* Your device sizes should be the same as you were instructed to attain in Lab 1a. Do not adjust rise and fall times by changing transistor sizes here. The rise and fall times will be different from the schematic.

* Attach inverter #1 cell layout as a "load" to the output of each cell prior to simulation. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell. Read the simulation output from the cell you are testing, not the load inverter.

* Insure when you create extracted view from the layout that you include all parasitic capacitances. (Set switches-->Extract_parasitic_caps)

* For the simulation use the same inputs in the same order as you did for the schematic simulations, including your worst-case simulations.

* Use a rise and fall time for the inputs signals of .05 ns.

* Note the rise and fall times at the outputs of each cell. You do not need to submit waveforms for the rise/fall time tests.

B. Change the temperature of the inverter #1 layout (go to ADEL-->Setup-->Temperature) in the SPECTRE simulation to 100 degrees C and resimulate. Compare your simulation results.

5. (15%) ASSEMBLY: Layout a small logic block that implements the Boolean function ab + cbd + ef using only your inverter #1 and NAND gate cells from Part 3. This exercise should help you tune your cells so that they can be connected easily into logic blocks for the final project. Be sure that inputs/outputs with the same name are connected on the layout. Do not simulate or resize devices. You do not need to submit a schematic.

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6. (5%) DOCUMENT: Submit your lab writeup. The lab writeup is worth 5% of the Lab 1b grade.

Turn in final transistor-level schematics, layouts and layout SPECTRE simulation inputs and outputs for all cells. Turn in the layout for the logic block. You do not need to simulate this block.

Lab Report Contents (in order):

1. Title page
2. Description of your layout methodology.
3. Layouts of gates, captured as images, making sure the images are high enough resolution so the grader can see layout details and inputs/outputs are labeled. Submit your final layout images without the load inverter attached to the output.
4. Table showing cell sizes (width of the cell, height of the cell and cell area for all the cell layouts). The cell area is the width times length of the bounding box of your layout.
5. Simulation waveforms for the cells.
6. Temperature simulation results.
7. Layout of the logic block, captured as an image.
8. Conclusions about the lab.
9. LVS results as separate files (see below).

Your lab report should be a pdf file. Please do not submit a .doc or .docx file. Name the report as follows: LastnameLab1.pdf

Include as separate files: Each file called si.out generated in a folder called LVS showing the results either match or mis-match for each cell layout. Be sure you rename the si.out file after each cell is verified to something like NAND2.out. Otherwise it will get overwritten.

Use the "tar function" on UNIX or zip your files to put all the files including the report into a single file. (See wikipedia for instructions on how to tar a file). Do not put into rar format. Students submitting multiple files will lose points. Your reports must be in pdf format.

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Instructions on how to print your layout images in color:

For layouts:

In the layout editing window:

File->Print

"Submit Plot" window will pop up.

You can choose plot with "header" or "notes" or disabled both

Click on Plot Options

"Plot Options" window will pop up.

‧ Display type: display

‧ Plotter Name: (change to) Generic 300 dpi Adobe Post Script Level 2 Plotter (for color images)

‧ Send Plot Only To File : (type in file name ending with .ps)

Then use distill function to convert .ps to .pdf

Another alternative is to use File-->Export Image. Be sure the grader can see enough details.

Submit the assignment using the Assignments function on the DEN blackboard.

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Some Guidance from the TA:

Please be sure to use alphabetic characters to begin signal names. Cadence might have trouble with names like /A or 3A.

Cadence is case sensitive. Case sensitive means that the labels in your schematic should be consistent with the labels in your layout. For example, if in my schematic I use A for the input of the inverter then in the layout I should use A for the input of the layout inverter (If I use a instead of A it won’t work).

The label for the power supply terminal in the layout should be vdd! (do not use Vdd!), for ground use gnd! (do not use Gnd!)

************ Rise/Fall time

There is an option in the rise time window that allows you to measure all the rise times in a simulation. It is the # of occurrences. The default is “single”, you can change it. If you couldn't compute the rise time or fall time using the calculator function, you can always measure it manually. It will take some practice until you get used to managing the functions.

************Transmission gate

It is necessary to put on the schematic a floating vdd and a floating gnd in order to compare the LVS because you have them in your layout (vdd!, gnd!).

*********** Flipping layouts:

In case you need to flip the layout cells you can do the following: select the cell--> right click-->rotate and then select the rotate option of your preference.

****** A final comment

If the layout/schematic does not match, please verify all the pins and all the connections on each node. Also, please remember to put ntap and ptap on the layout. If you couldn't find the errors, then I suggest to repeat the layout again, though 99.9% of the time the LVS error is due to a wrong connection or wrong pin labels. These cells are small enough to be able to find the error. You can use the help of the LVS output file to identify the error.

Before sending the TA emails please try all the possible options and verify all possible layout/schematic errors. Do not send schematic/layout images by email unless told to do so..

Good luck!