University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #1a

Logic Gate Design and Simulation Experiments

with Combinational Cells

Due 3/3/17, 5:00 PM Via the DEN Online Assignment Function (100 points, worth 4% of final grade)

YOU MUST WORK INDEPENDENTLY ON THE LABS: THERE ARE NO PROJECT GROUPS


1. (54%) CIRCUIT DESIGN: Use CADENCE Virtuoso schematic capture to design complementary CMOS logic gates at the transistor circuit level for the following functions:

  1. 3 inverters,
  2. transmission gate,
  3. 2-input NAND,
  4. 4-input NAND, and
  5. a compound gate that implements the function COMPOUT = NOT {[A+B+C]*D*[E+F]* [H+I]}

SIZING RULES:

Your lab technology lambda is 100 nm. Assume Vdd = 1.8v. For your schematic and layout you must make the transistor dimensions in multiples of .5 lambda.

A. The Basic Inverter #1: The NMOS transistors in the inverter should be "unit" sized, as defined in the text and lectures, and the PMOS transistors should be 2 times as wide. This might not result in rise time = fall time.


B. The Larger Inverter #2: Size both the transistors in this inverter 5 times as wide as in the basic inverter transistors. Remember that you can put two or more unit-sized transistors in parallel in place of widening a single transistor if it helps keep your methodology consistent.


C. The Largest Inverter #3: Size both the transistors in this inverter 5 times as wide as Inverter #2. For inverter #3, experimentally perform a rough estimate for transistor k (beta) ratio by looking at rise and fall times.


D. The Transmission gates: Size the transistors the same as the inverter #1 transistors.


E. The NAND gates: For the 2-input and 4-input NAND gates, use unit size NMOS transistors and make the PMOS transistors wide enough to have rise and fall times within 30% of each other in the worst case. In other words, rise time < 1.3 x fall time or fall time < 1.3 x rise time.


F. The compound gate: For the compound gate, experiment with transistor widths that give output rise and fall times within 30% of each other, in the worst case. Note that the sequence of inputs that give worst-case timing might be different from the required input sequences specified below. Note also that when you have adjusted the critical path, other paths may need adjustment as well. Worst-case timing and critical paths will be discussed in class. You can manipulate the Boolean equation as desired. Include your choice of worst-case path in your discussion.

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2. (40%) SIMULATION: a) Simulate your transistor circuits (Cadence circuits) using SPECTRE to determine that they function properly, and to obtain information for device sizing as described above.

SIMULATION RULES:

* Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label your outputs INV1OUT, NAND2OUT, etc.


* Attach your inverter #1 design to the output of each gate (including the inverter) prior to circuit extraction and simulation to provide a load capacitance. The output you should plot is the input to this load inverter.


* Simulation timing: Assume .05ns rise and fall time for your inputs. Hold all input values stable for at least 1.8ns.


* Show simulations of each gate with all possible combinations of inputs.


* Change the inputs in the following manner:

4-input NAND: ABCD = 0000, ABCD = 0001, ABCD = 0010....etc.


2-input NAND: For the 2-input gates AB = 00, AB = 01, etc.


Compound gate: For the compound gate, simulate all combinations of A, D, E and H from 0000 to 1111, counting up in binary 0000, 0001, 0010, etc. , while holding all other inputs to 0.



In another test, hold ABC=010 and DHI to 111, and then change EF from 00 to 11, counting up as before.{[A+B+C]*D*[E+F]* [H+I]}


Please change the inputs in the order given so that we can grade what you are doing easily.


SIMULATION INSTRUCTIONS:


a) Simulate all designs.


b) For inverter #1 and inverter #3, increase the input voltage starting at 0.0v until the output begins falling (theoretically until the slope of the input/output transfer curve = -1 so use visual inspection, but measuring this is not easy). Then find the low noise margin, assuming VOLMAX = 0.0v. Find the high noise margin in a similar way.



Note: Low noise margin is defined as NML= VIL-VOLmax, assume VOLmax=0.0v.

High noise margin is defined as NMH= VOHmin-VIH, assume VOHmin=Vdd.


To estimate VIL and VIH so that you can compute the noise margin values, you could approximate the voltages when you see the output begins changing or find the -1 slopes on the input-output transfer curve.


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6. (6%) DOCUMENT: Submit your lab writeup. The lab writeup is worth 6% of the Lab 1 grade.

Turn in final transistor-level schematics and schematic SPECTRE simulation inputs and outputs for all cells.

Lab Report Contents (in order):

  1. Title page
  2. Transistor schematics of gates taken from Cadence. Submit your final schematic images without the load inverter attached to the output.
  3. Discussion and explanation of how you sized transistors, and the beta ratio you found, including measured rise and fall times.
  4. SPECTRE input and output waveforms for each gate schematic transient simulation in the form of images showing the waveforms.
  5. Images of the Vout-Vin transfer curve and results of the noise margin computations
  6. Conclusions about the lab, especially about sizing the transistors in the compound gate.

Your lab report should be a pdf file. Please do not submit a .doc or .docx file.


Use the "tar function" on UNIX or the Zip function to put all the files including the report into a single file. Do not put into rar format. Students submitting multiple files will lose points. Your reports must be in pdf format and zipped with the other files.


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Instructions on how to print your waveform images in color:


To get pictures from Cadence in your report:


For schematics: Use File-->Export Image. Enter a name and save as PNG


For waveforms: Please click on them, otherwise they are very hard to see.

File -> Save Image -> Image Options -> Create exact copy of window

Then enter a name and save in PNG format.

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Some Guidance from the TA:


Please be sure to use alphabetic characters to begin signal names. Cadence might have trouble with names like /A or 3A.


Cadence is case sensitive. Case sensitive means that the labels in your schematic should be consistent with the labels in your layout. For example, if in my schematic I use A for the input of the inverter then in the layout I should use A for the input of the layout inverter (If I use a instead of A it won’t work).


************ Rise/Fall time

There is an option in the rise time window that allows you to measure all the rise times in a simulation. It is the # of occurrences. The default is “single”, you can change it. If you couldn't compute the rise time or fall time using the calculator function, you can always measure it manually. It will take some practice until you get used to managing the calculator.


Good luck!