EE477 - s17 hw5

Homework Assignment #5

E477 Spring 2017 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 10 AM 4/10/17

OR Ecopies due 10 AM 4/10/17 using the "Assignment" Function on DEN

Assume lambda is .1 microns. Assume Vdd is 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V.

Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns.

You can use these values for transistor betas: _n (beta)= 219.4 W/L _ A(microamps)/V² and _p (beta)= 51 W/L _ A/V² .

e₀ (epsilon) = 8.85 X 10 ^-14 F/cm, e__oxide(epsilon) = 3.9*_₀, and e__silicon(epsilon) = 11.7*_₀.

N_A=4X10¹⁸cm^-3 (substrate doping)

N_D=2X10²⁰ cm^-3 (source/drain doping)

N_A(sw)=8X10¹⁹ cm^-3 (Sidewall (p+) doping)

n_i²= 2.1X10²⁰ cm^-3 (intrinsic carrier concentration of silicon)

x_j (diffusion depth) =32 nm

KT/q= .026 V (thermal voltage)

Cjbsn = 17.27 x 10-4 pF/ μm2 and Cjbswn = 4.17 x 10-4 pF/ μm (micrometer).

Cjbsp = 18.8 x 10-4 pF/ μm2and Cjbswp = 3.17 x 10-4 pF/ μm (micrometer).

1) (15%) Compute the worst-case rising and falling RC time constants at point B of the circuit below using the Elmore delay method. Assume all transistors are unit sized and wire capacitance is lumped. Assume Rchn = 2000 ohms. Cg(n+p) = 20 ff, Cd(n+p) = 20ff, and Cint = 10 ff. Rint for interconnect1 is 10 ohms, interconnect2 is 5 ohms, and interconnect3 is 7 ohms.

2 a) (15%) Is CBADEFGHIBACAGD an Euler path for the PMOS transistors shown in the circuit below. If so, mark it. If not, mark where it fails.

b)(5%) What information does an Euler path tell you about transistor placement when laying out a compound gate?

c)(10%) Circle all the diffusion capacitance locations that could contribute to fall time, even if some do not when the longest path is on for discharge.

3 (10%) Assume you have the following wires to place in a layout. The numbers give starting and ending x positions of the wires. Place them using the Left Edge algorithm. Two wires in the same track can start and end at the same point. So a wire can end at 4 and another can start at 4.

3,7 4,6 1,5 2,4 5,7 3,8 1,6 6,8

4) (8%) Compute the gate capacitance for an NMOS transistor in linear and saturation region. The NMOS transistor dimensions are: W=9 lambda, L= 3 lambda. Assume L_D=0.0 nm.

5) (8%) Use the fringing field figure on p. 274 of the text. Assume w/l = 0.2, and w/h = 0.5. Estimate the fringing field factor if t/h = 1.

6) (8%) Assume electrons in a wire on a CMOS chip move at v m/sec and the rise/fall time on the wire is 0.01ns. Assuming wire length is 1 cm, what electron velocity would require us to consider inductance?

7) (8%) Ernie Engineer decides to separate the first and second latches of a negative edge-triggered flip flop by a long wire so he can fit the flip flop into little spaces in a complicated layout. Now he finds he needs to increase his clock period. Explain what timing of the flip flop is affected by the long wire? t_holdis the hold time, t_setup is the setup time, t_q is the clock-to-Q time, t_L2prop is the propagation delay in the feedback path of the second latch, and t_comb is the propagation delay of the feedback combinational logic.

8) (8%) Compute the Cdp for the source diffusion sidewall that faces the channel of a unit size PMOS transistor. Use the diffusion capacitances given above Cjbsp = 18.8 x 10-4 pF/ μm2and Cjbswp = 3.17 x 10-4 pF/ μm (micrometer).

9) (5%) Calculate the resistance of a wire .03 cm long and 6 lambda wide that has resistance .4 ohms/square.