EE477 - s17 hw4

Homework Assignment #4

EE477, Spring 2017 Due 3/30/17 5 PM

Assume for the problems below that V_dd = 1.8 V, V_tp0 is -0.4 V. and V_tn0 is 0.4 V. V_tpbodyeffect is -0.55 V. and V_tnbodyeffect is 0.55 V.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

lambda = 100nm

1. (5%) What design rule prevents shorts between source and drain in a transistor?

2. The input signal and corresponding output signal for an inverter are shown below.

a. (5%) An output signal rises from 0.0v to 1.8v in 1.0ns. What is the rise time of the output if it rises linearly?

b. (5%) An inpug signal falls linearly from 1.8v to 0.0v in .8ns. What is the fall time of the input?

c. (5%) What signals do you need to know to compute the rising delay of an inverter?

3. (10%) Sketch the steps involved in patterning vias between metal1 and metal2 using a positive photoresistance.

4. (10%) List the steps required for creating a PMOS transistor, and draw a crosssection of the PMOS transistor, labeling each layer/feature in the order fabricated.

5. (10%) Ernie Engineer forgets to put Ntaps in his NWells. What happens to his circuit when he applies Vdd and Gnd?

6. (10%) Where do we find thin oxide in a CMOS circuit? Why don't we use thick oxide?

7. (10%) CMOS uses a self-aligning gate process. What does this mean?

8. (10%) What parasitic transistor can form between a P- substrate, an NWell, and a P+ diffusion in the NWell?

9. (20%) Draw the crosssection indicated by the dashed line on the layout below and label all the layers.