Homework Assignment #3
EE 477 Spring 2017 Professor Parker
Hardcopies due in EE 477 box in EEB Basement 5 PM Feb 17, 2017
OR Ecopies due 8 PM Feb 17, 2017 using Assignment Dropbox on DEN (there are scanners in SAL)
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.
Question 1:
a) (8%) Define the terms VOHmin, VIHmin, VILmax and VOLmax, and arrange them from lowest value to highest value.
b) (8%) Suppose you want to achieve maximum noise margin and you can change each of the above values individually while keeping the others fixed. Which ones would you increase and which ones would you decrease?
Example: If VIHmin, VILmax and VOLmax are constant, VOHmin should increase/decrease? (Do this for all 4)
c) (4%) If you could get an ideal inverter in this technology, what would be the numerical values for VOHmin, VIHmin, VILmax and VOLmax? Hint: An ideal inverter voltage transfer curve looks like a unit step.
Question 2: (12%) The diagram shows a 2-input NOR gate. A) Identify the inputs setting up your worst case rise and fall times by discharging/charging all transistors. B) Then, identify the input transition leading to worst case rise time and the one leading to worst case fall time. Explain why you chose these transitions.
Your answer for each case in B should be a single transition, like you would do in Cadence. 1 input should be fixed while the other changes value.
Question 3: Consider the logic function X = ~[(A.B)+(C+D).(E+F+G)] realized using this compound gate:
a) (10%) Locate all the drain and source capacitances of all the NMOS and PMOS which will be charged/discharged.
b) (10%) Identify the critical path leading to worst case rise time. Clearly mention the logic level of each input. Your answer should only give the final logic levels of all inputs, transition is not required. Do all capacitors get charged?
c) (10%) Repeat part b) for worst case fall time. Do all capacitors get discharged?
Question 4: The first diagram shows a Cadence inverter setup to do DC analysis, as shown in the discussion classes. Both the NMOS and PMOS have width = 300 nm and length = 200 nm. The second diagram shows results of the DC analysis: Vout vs Vin (top) and current vs Vin (bottom). Note that Vin = 678 mV corresponds to Vout = Vdd/2 = 900 mV. This value of Vin also gives a spike in current.
a) (2%) What region is each transistor in when Vin = 678 mV?
b) (3%) What can you conclude about the relation between Kp and Kn?
c) (3%) Which is greater – rise time or fall time?
d) (6%) The beta ratio for this technology is given to be 4. How can you improve your design to make rise time and fall time almost equal?
Question 5:
a) (8%) Visually inspect the Vout vs Vin curve from Q4 and estimate both the noise margins. Assume VOHmin = 1.8 V and VOLmax = 0 V.
If you can’t see the x-axis properly: The x-axis major markings are at every 0.3 V, starting from 0 up till 1.8. Each major interval has 5 minor markings, so each minor interval = 0.06 V. Approximate answers for noise margins are fine.
b) (6%)The width of the NMOS transistor is now increased from 300 nm to 600 nm. What is the effect on NMH and NML (do they increase/decrease)?
Question 6: Consider a 2-input XOR gate. It’s logic equation can be written in 2 ways:
Option 1: A XOR B = A.(~B) + (~A).B -> Sum-of-products uses 2-input NAND gates
Option 2: A XOR B = (A + B) . (~A + ~B) -> Product-of-sums uses 2-input NOR gates
a) (8%) Assume beta ratio = 4 and all NMOS transistors have width = 300 nm. You need to design 2-input NAND and 2-input NOR gates so that worst case rise time = worst case fall time. Calculate the width of PMOS for the NAND and NOR.
b) (2%) Which option of XOR is better for achieving a small design?