Homework Assignment #1

EE 477 Spring 2017 Professor Parker

Hardcopies due in EE 477 box in EEB Basement 5 PM Jan. 31, 2017

OR Ecopies due 5 PM Jan. 31, 2017 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

Note: + implies OR, . implies AND, ~ implies NOT

Question 1:

a) (4%) Use transmission gates to design a 3-input OR gate

b) (11%) Now use transmission gates to construct the following function: F = (A+B+C).(D+E)

Question 2:

a) (11%) Use transmission gates to design a custom multiplexer with select signals S0, S1, inputs A, B, C, D, and output Out.

b) (4%) Now suppose input A is always logic 0 and B is always logic 1. Can you make the circuit simpler?

Question 3: Consider the function: X = A.B.C.D + E.F.G.H

a) (4%) Draw its logic gate diagram using negative gates only (NAND, NOR, INV):

b) (8%) Draw the stick diagram of each unique gate you have used above (i.e. if you have used 2 gates of the same type, just draw the stick diagram once).

c) (5%) Draw a compound gate transistor level diagram of X

Question 4:

a) (4%) Suppose you have a design constraint that your gates can have a maximum of 2 inputs. Redraw the logic gate diagram of X in problem 3 using negative gates only.

b) (6%) Redraw the logic gate diagram of X using positive gates only (AND, OR) and the same constraint - gates can have a maximum of 2 inputs.

Notice the difference between positive and negative logic when decomposing a big gate into smaller gates.

Question 5:

a) (3%) Show the truth table for a 2-input XOR gate and give its logic equation: A XOR B = ?

b) (10%) A 3-bit parity checker counts the number of 1’s in a sequence of 3 bits and outputs 1 if odd, 0 if even. (Example: If the input is 101, output is 0, but if the input is 001, output is 1).

Design this circuit using XOR gates built using negative gates only and draw the transistor level diagram. You can assume that negative inputs like ~A are available.

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Question 6: (10%) Consider the following 2-to-1 MUX built using transmission gates as shown in class. The ~pickX signal is generated from an inverter which has a delay of 2 time units. Look at the given timing diagram and draw the waveform for Out from beginning to end. Is there any period of time when Out isn’t well defined?