EE477 - s14 lab3 part2

Part II: The Digital Neuron

This part of the lab is the design of a special-purpose digital circuit that mimics a neuron (brain cell). Be sure to finish and test your schematic of the neuron before you start the neuron layout.

There are 10 inputs to the neuron:

10 single-bit data inputs to the neuron, P, Q, R, S, T, U, V, W, Y, Z that could be different every clock cycle
a single-bit inhibitory input I,
Load control signal, that allows the output ff to be loaded with a new value,
Reset control signal
and a clock with 50% duty cycle.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

Each data input and control input has a single bit.
The inhibitory input I is a single bit.
The neuron output contains one firing flip-flop you designed in Lab 2, and the output of the flip-flop AP represents the output of the neuron.
The neuron "fires" when at least three out of 10 data inputs P, Q, R, S, T, U, V, W, Y, Z are equal to 1, and I is NOT equal to 1. The firing test logic is combinational.
After the negative edge of the clock, if the neuron fires, the output of the firing flip-flop goes from low to high. The output remains high until the next falling clock, when it is lowered if the new inputs do not cause a "1" to be loaded into the FF.
Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
Note that you might find a way to use the compound gate you designed in Lab 1, and you might need more than one of these gates. You do not have to use it at all.

A block diagram of the neuron is shown below.

The Laboratory Steps for Part II:

1. Design your neuron circuit and create a Cadence circuit (schematic) diagram using the circuits/cells you have designed in Labs 1 and 2. You cannot design new cells for Lab 3. Include your logic/gate level diagram for your neuron.

2. Simulate your neuron schematic to ensure that your design works correctly. Use the following sequence of inputs for initial testing of your schematic:

a) Set load to 1 and keep it high. All other inputs except clock should be 0, including I. Reset your neuron flip flop.

b) Set load to 1 and keep it high, while keeping I = 0. Then test your neuron by sequencing through all combinations of inputs starting with PQRSTUVWYZ= 0000000000 to 0000011111 (32 values), then run a separate simulation with inputs 1100000000 and 1110000000 (2 different values).

c) Now set I = 1 (inhibition), leave load =1 and sequence through the same inputs. The output AP should be low.

d) Reset the neuron flip flop. Now set load to 0 (zero). Set the 10 data inputs to 1111111111, and I = 0. The flipflop output should remain zero.

3. Lay out your neuron.

4. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected to each other.

5. Simulate your neuron layout with SPECTRE to ensure that your design works correctly using the same sequence of inputs as in Step 2, and measure the smallest clock period for the neuron. Show the waveforms you used to measure the clock period.

You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes. Again measure the smallest clock period for the neuron.

Testing Strategy:

Here is a testing strategy that might be useful to you: Design the schematic first and test. Then design the layout and test each part as you build it.

Design and test at each stage. Design the output flip-flop first. Then design the logic and the output of the logic that makes the neuron fire if the logic creates a "fire" situation. Test the logic separately first. Then add the flip-flop. Then test the entire neuron.

Include in this part of the lab report, in order:

A description of the neuron you built, including a transistor-level and gate-level circuit diagram (schematic) printed from Cadence, your simulation results and a description of how your circuit was constructed using existing cells.
A floorplan of the neuron layout. A floorplan shows where on the layout you placed functions, without showing the details of the functions. Cadence might have a tool to do this for you but you need to draw it yourself for clarity. Try this link to see an example. You do not have to draw your floorplan over your layout image but it helps clarity.
Your neuron layout image and neuron layout simulation results as images. Make sure the layout and simulation images are of high enough resolution so that we can zoom in to check things. Put your input and output waveforms onto multiple graphs so we can read them more easily
A description of the simulation experiments you ran with SPECTRE for the neuron.
SPECTRE outputs (waveforms) for the neuron schematic and layout.

Include (not in the report but as separate files)

1. SPECTRE netlist files for both schematic and layout of the neuron, generated by Cadence, which will include the technology file, the graphical stimulus files and the circuitry netlist. We need everything you used so that we can run your simulations in case your results are unexpected.

2. High resolution images of your neuron layout. This is so we can view the layout properly to check details.