EE477 - s14 lab3 complete

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 (worth 20% of final grade)

Module Design, Cadence and SPECTRE

Due 5/5/14 4:59 PM

There will be no extensions so plan your time accordingly!

Required contents of the report appear in purple.

This is a long lab so be sure you scroll to the end to see all the information.

Rules:

You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have to design circuits to generate the other clocks.
You need to generate all inverted inputs, including /clock. /load is not an input to the circuit. You need to generate it if you need it.
You must use the cells you designed in labs 1 and 2 to build your neuron and your neural network. Do not change the circuit structure of your cells unless your cells do not meet the requirements of lab 1 or 2 (i.e. you lost points). You can rearrange the layout slightly or resize transistors as needed. Do not change the methodology by rotating transistors, rearranging transistors, connecting inside the cell on different layers, or changing your interconnection strategy (for example, you might decide that all inputs come in the top of the cell, so you can't change that). You can move ntaps and ptaps around.
You must have ntaps and ptaps according to the rules. Make sure your ohmic contacts (ntaps and ptaps) meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course the taps should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts, as Cadence will do for you automatically.
You can tune the circuits by changing transistor sizes as needed or to squeeze out empty space.
You cannot remove unused inputs or unused logic from your cells.
You can use metal layers 1-4 for the neuron and any buffering, and layers 1-6 for any external connections that go to other neurons, to Vdd, to buffers, and other connections outside the neuron.
All signals should use the names we have given below.
As in Lab 2, the output transition of the flip flop should occur before the next rising clock. Clock to Q and combinational logic delay should occur between the falling edge of the clock and the next rising edge.
For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected.
On your layout, all inputs and outputs to the circuit must be routed to the edges of the layout and must be labeled using the pin name.

Include a title page in your report that includes your name and student number. Your report file name should be Lastnameusernamelab3.pdf. Do not submit other file formats, like .doc, .txt.

At the beginning of your report, please give the final area and delay of your final design from Part III, and your final area*delay product.

Part I: Superbuffer Design

Design a super buffer (circuit schematic) that drives a large load through a long wire. We expect the total capacitive load to be 100pf and the total wiring resistance to be 800 ohms, and assume C_gn+C_gp = 2.5ff for inverter #1. Assume the super buffer is driven by an inverter like your inverter #1 from Lab Assignment 1. Be sure to use an even number of stages for the super buffer. You can alter transistor sizes of your existing inverters to use in the super buffer. Test your super buffer schematic with inverter #1 as input and with output resistance and capacitance given here. In your report, show the super buffer schematic and give the number of stages and device sizing used, and how you arrived at this design. Show the waveform for rising and falling output measured at node Out, and report the rise/fall times (10%-90% and 90% to 10%). Do not resize your inverter #1 unless it was incorrect in Lab 1. You might want to use this design in Part III.

Part II: The Digital Neuron

This part of the lab is the design of a special-purpose digital circuit that mimics a neuron (brain cell). Be sure to finish and test your schematic of the neuron before you start the neuron layout.

There are 10 inputs to the neuron:

10 single-bit data inputs to the neuron, P, Q, R, S, T, U, V, W, Y, Z that could be different every clock cycle
a single-bit inhibitory input I,
Load control signal, that allows the output ff to be loaded with a new value,
Reset control signal
and a clock with 50% duty cycle.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

Each data input and control input has a single bit.
The inhibitory input I is a single bit.
The neuron output contains one firing flip-flop you designed in Lab 2, and the output of the flip-flop AP represents the output of the neuron.
The neuron "fires" when at least three out of 10 data inputs P, Q, R, S, T, U, V, W, Y, Z are equal to 1, and I is NOT equal to 1. The firing test logic is combinational.
After the negative edge of the clock, if the neuron fires, the output of the firing flip-flop goes from low to high. The output remains high until the next falling clock, when it is lowered if the new inputs do not cause a "1" to be loaded into the FF.
Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
Note that you might find a way to use the compound gate you designed in Lab 1, and you might need more than one of these gates. You do not have to use it at all.

A block diagram of the neuron is shown below.

The Laboratory Steps for Part II:

1. Design your neuron circuit and create a Cadence circuit (schematic) diagram using the circuits/cells you have designed in Labs 1 and 2. You cannot design new cells for Lab 3. Include your logic/gate level diagram for your neuron.

2. Simulate your neuron schematic to ensure that your design works correctly. Use the following sequence of inputs for initial testing of your schematic:

a) Set load to 1 and keep it high. All other inputs except clock should be 0, including I. Reset your neuron flip flop.

b) Set load to 1 and keep it high, while keeping I = 0. Then test your neuron by sequencing through all combinations of inputs starting with PQRSTUVWYZ= 0000000000 to 0000011111 (32 values), then run a separate simulation with inputs 1100000000 and 1110000000 (2 different values).

c) Now set I = 1 (inhibition), leave load =1 and sequence through the same inputs. The output AP should be low.

d) Reset the neuron flip flop. Now set load to 0 (zero). Set the 10 data inputs to 1111111111, and I = 0. The flipflop output should remain zero.

3. Lay out your neuron.

4. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected to each other.

5. Simulate your neuron layout with SPECTRE to ensure that your design works correctly using the same sequence of inputs as in Step 2, and measure the smallest clock period for the neuron. Show the waveforms you used to measure the clock period.

You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes. Again measure the smallest clock period for the neuron.

Testing Strategy:

Here is a testing strategy that might be useful to you: Design the schematic first and test. Then design the layout and test each part as you build it.

Design and test at each stage. Design the output flip-flop first. Then design the logic and the output of the logic that makes the neuron fire if the logic creates a "fire" situation. Test the logic separately first. Then add the flip-flop. Then test the entire neuron.

Include in this part of the lab report, in order:

A description of the neuron you built, including a transistor-level and gate-level circuit diagram (schematic) printed from Cadence, your simulation results and a description of how your circuit was constructed using existing cells.
A floorplan of the neuron layout. A floorplan shows where on the layout you placed functions, without showing the details of the functions. Cadence might have a tool to do this for you but you need to draw it yourself for clarity. Try this link to see an example. You do not have to draw your floorplan over your layout image but it helps clarity.
Your neuron layout image and neuron layout simulation results as images. Make sure the layout and simulation images are of high enough resolution so that we can zoom in to check things. Put your input and output waveforms onto multiple graphs so we can read them more easily
A description of the simulation experiments you ran with SPECTRE for the neuron.
SPECTRE outputs (waveforms) for the neuron schematic and layout.

Include (not in the report but as separate files)

1. SPECTRE netlist files for both schematic and layout of the neuron, generated by Cadence, which will include the technology file, the graphical stimulus files and the circuitry netlist. We need everything you used so that we can run your simulations in case your results are unexpected.

2. High resolution images of your neuron layout. This is so we can view the layout properly to check details.

Part III: Building the Small Neuron Network

You will produce a working schematic and layout for a small neural network with 11 actual neurons, 1 main neuron and 10 others, including any buffers you attach to the neurons. If you use a superbuffer on the main neuron you should use the same one on all the neurons. You can use the super buffer from Part I, or any of the stages of the super buffer from Part I, as long as you use the stages in order, starting with the smallest, and making sure you have an even number of stages. Larger super buffers will consume more area. The goal is to minimize the area·delay product of the neural network and its output buffers, if any. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com.

The Laboratory Steps:

1. Use the neuron you built in Part II. Lay out the super buffer you want to use and add it to the neuron layout to make a single block. Show the combined layout of the neuron and super buffer in your lab report. Simulate this block to ensure it operates properly and show simulation results.

2. Floorplan the Network: As you are laying out the neuron and the super buffer you have designed, plan how you would fit all the neurons together with a floorplan showing a block of 11 neurons, one of which is your main neuron. Inputs to your main neuron will come from primary inputs to your circuit, and all 10 neurons will receive the AP output from the main neuron to all their data inputs. The I inputs to all neurons are external to the network and are inputs to your circuit. You can tie them together at the border of the layout to make simulations easier. Square layouts tend to have shorter wires than long narrow layouts. The block diagram shown below describes how to connect the neurons.

3. Layout this network of neurons.

Simulate the entire network, resetting all flip flops, then set enough inputs to the main neuron to 1 so that it will set its flip flop. All other neurons should be set in the next cycle. I = 0 for all neurons. Be sure to draw a schematic and run LVS to ensure your layout is the correct design.

4. To check performance, simulate your entire neural network layout, and make sure that each neuron getting an input from the main neuron receives its input in time; this determines the clock period for the entire network layout. Test the main neuron sending a 1, and then sending a 0 to test rise and fall times. Please notice the information about the exact delay you should measure given below.

Discussion

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. Pay close attention to the specific delay you are to measure.

The delay you should measure with SPECTRE simulations of your layout for your final result is the clock cycle or clock period assuming correct data gets to every neuron in time(see step 4 above). Your outputs should appear during the measured cycle (before the clock rises again). The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock period. If you compute the area-delay product wrong, or you do not compute it you will lose points.

Upload your report to the assignments function of Blackboard, including your layout and simulation files as a TAR file so that we can test (simulate) your circuit to be sure it performs as specified. SPECTRE netlist files for layout of the neuron, generated by Cadence, which will include the technology file, the graphical stimulus files and the circuitry netlist. We need everything you used so that we can run your simulations in case your results are unexpected.

Include in Part III of the report:

Neuron + buffer layout and simulation.
Schematic of the neural network.
Layout image of the neural network, along with simulation results of the network showing the clock period, along with LVS result for the neural network.
A discussion of any design changes you implemented to improve performance.

Final Report:

All items from Parts I, II and III except files to be attached should be in a single report. Tar this report along with the files specified above and upload to the assignments page of the blackboard.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.

End of Lab 3