EE477 - s14 lab2 part2

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2 Part2

Latch/FF Design, Layout and SPECTRE Simulations

Due April 7, 2014, 4:59 PM

Changes marked in blue 3/24/14

V_dd = 1.8 V.

Part 2: LATCH and FLIP-FLOP DESIGN 70%

********************************************* NOTES FOR SCHEMATIC AND LAYOUT PARTS***********************************

For the schematic and layout simulations follow the following notes:

Note 1: Attach your inverter#1 as a "load" to the flip-flop output. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell.

Note 2: The clock and all input signals should have a rise and fall time of .1 ns.

Note 3: The clock should have a 50% duty cycle.

Note 4: Proper functioning of a flip flop includes having the low output be less than .1 V_dd and the high output being greater than .9 V_dd.

Note 5: The inputs to the flip flops are: clock, /clock, Data D, asynchronous reset, synchronous Load and synchronous /Load.

Note 6: The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop).

Note 7: The transistors in the gates used in the flip-flop should be sized as they were sized for Lab 1.

Note 8: Do not use ratioed (pseudoNMOS) logic. Do not use dynamic logic or dynamic storage (not covered yet).

Note 9: A note about well and substrate contacts (ntap and ptap): Make sure your ohmic contacts meet the following requirement:

* Every cell should have a well and substrate contact.

* For larger cells, include at least two ohmic contacts per 50x50 lambda square, one for the p-substrate and the other for the n-well, assuming there are both NMOS and PMOS transistors in the space.

* Every separate block of n-well should have at least one ohmic contact.

* For all your contacts, you will get the best design if you use multiple minimum-size contacts for large contact areas and not large contacts. Cadence will do this automatically for you if you try to use large contacts.

************************************************SCHEMATIC**********************************************************

A. SCHEMATIC for D flip flop:

Use only the cells you have already constructed to design a latch, and use two latches to build a CMOS D flip-flop schematic in Cadence.

Design the two latches as separate cells and then place them together to form the flip-flop. You can use one of the larger inverters in one or more places in the flip flop if it gives you a faster design.

Assume the flip-flop is clocked and can be asynchronously reset.

clock, /clock, Data D, asynchronous reset, synchronous Load and synchronous /Load are inputs to your design.

Load is active high.

When Load is low, the data will recirculate, regardless of the clock.

The flip-flop should be negative edge triggered.

B. SCHEMATIC Simulations for the flip-flop you built in Cadence using SPECTRE

1) Be sure to try all possible combinations of data inputs versus present state of the flip flop, including the waveforms shown below. Note: This is a functionality test, you can do it with a slow clock frequency.

2) Be sure you test reset. Start with clock low, D high and Load low. Note: Reset is asynchronous, that means that independent of whether the clock is high or low when reset is active the output goes to 0 V and 0 is stored in the flip

flop. In this test you should show that when reset is enabled, the output does not follow Data D instead it goes to 0 V.

3) Adjust the timing of your clock to be as fast as possible and still have your flip flop work properly. Use the waveform below to perform this test. Note: Make sure the inputs have settled a setup time before the clock edge.

4) Measure the setup time. The setup time is the amount of time before the falling edge of the clock that input D must be stable (the time difference between the 50% of the Data D voltage range and the 50% of the clock voltage range).

Note: The waveforms shown below show the order of changes of inputs you are to use for the simulations.

**************************************************LAYOUT*********************************************************

C. LAYOUT the flip flop:

Use the same layout methodology you used in Lab #1, using only the bottom three layers of metal 1, metal 2 and metal 3.

Suggestion: At this point if you have routing problems you may need to adjust the layout routing slightly. If you do adjust your cells, describe it in your report.

D. LAYOUT Simulations for the flip-flop you built in Cadence using SPECTRE

For the layout simulations, be sure to follow notes 1-9

1) Repeat the same simulations you performed for the schematic part B.

2) Note the delay between V_in (D) changing and V_out(Q) changing.

Use the definitions of delay given in the text as the time between the input achieving 50% of its final value and the output achieving 50% of its final value. This will give us the sum of the setup and clock-to-Q times, with setup the time before the clock,

and clock-to-Q the time after the clock. Note: You should measure two values, one for the output falling transition and another for the output rising transition. ~~For this part, you can use either the waveform above or your own test setup.~~ For this part, the clock frequency should be maximum, the data transition should complete a setup time before clock falls.

The waveform shown in lab2 may not test both inputs/outputs transitions, so you may need additional input combinations for this measurement.

3) Measure the setup time. The setup time is the amount of time before the falling edge of the clock that input D must be stable (the time difference between the 50% of the Data D voltage range and 50% of the clock voltage range).

********************************************SUBMISSION PART**************************************************************

What to turn in for Part 2:

Your Lab 2 part 2 (in pdf format) should contain the following items:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number (2%).
A description of the flip-flop you built, including a transistor-level or gate-level circuit diagram printed from Cadence (18%).
The latches and flip-flop layout screen captures. Make sure to show the pin names (15%).
A description of all the simulation experiments you ran with SPECTRE (5%).
Submit all the waveforms for the flip-flop schematic and layout. Show waveforms for all the simulation experiments including the measurements of the reported values in items 6 and 7. Put your input and output waveforms onto multiple graphs so we can read them more easily (30%).
Report the values for schematic: clock maximum speed, setup time.
Report the values for layout: clock maximum speed, setup time, and the delay between V_in changing and V_out(Q) changing.

Items 1-7 should all be in a single report. Tar this report along with the SPECTRE netlists - these should not appear in the report, but be submitted as separate files, tarred with the reports and the items from part 1 of this lab, and upload to the assignments page of the blackboard.

Do not put the SPECTRE netlists into the report itself.

Note: We only need the netlist files for the schematic and the layout of your final D-flip flop.

Netlist files can be obtained in the ADE L (simulator window) go to simulation--> netlist--> display

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. You will have two chances to upload your files. All files for Part 1 and Part 2 and both reports should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color except with permission of the instructors. Failure to follow these instructions could result in deduction of points.

LAB Hint: Do not name files or cells starting with a number - like 4inputnand. Cadence and/or SPECTRE might have trouble with this. They might also have trouble with names like /clk, so use notclk instead.