University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2 PART 1

Latch/FF Design, Layout and SPECTRE Simulations

Due April 7, 2014, 4:59 PM

V_dd = 1.8 v.

Note: Yilda is on break this week. Please contact me first if you have questions about this lab.

A note about well and substrate contacts (ntap and ptap): Make sure your ohmic contacts meet the following requirement:

* Every cell should have a well and substrate contact.

* For larger cells, include at least two ohmic contacts per 50x50 lambda square, one for the p-substrate and the other for the n-well, assuming there are both NMOS and PMOS transistors in the space.

* Every separate block of n-well should have at least one ohmic contact.

* For all your contacts, you will get the best design if you use multiple minimum-size contacts for large contact areas and not large contacts. Cadence will do this automatically for you if you try to use large contacts.

Part 1: Lab 1 Cell Layout SPECTRE Simulations 30%

A. Simulate the cell layouts you designed in Lab 1 using SPECTRE (inverters, NANDs, transmission gate and compound gate).

* Your device sizes should be the same as you were instructed to attain in Lab 1. Do not adjust rise and fall times by changing transistor sizes here. The rise and fall times will be different. You can only change the cells from lab 1 by modifying the routing, cell width or cell height.

* Attach the smallest inverter cell layout as a "load" to the output of each cell. (Ideally you should test with the same size inverter you used in lab 1, not with the smallest inverter. If you have already run the tests with the smallest inverter you do not have to rerun them.) To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell. Read the simulation output from the cell you are testing, not the load inverter.

* Insure when you create extracted view from the layout that you include all parasitic capacitances. (Set switches-->Extract_parasitic_caps)

* For the simulation use the same inputs in the same order as you did for the schematic simulations, including your worst-case simulations.

* Use a rise and fall time for the inputs signals of .1 ns.

* Note the rise and fall times at the outputs of each cell.

B. Change the temperature of the smallest inverter layout (go to ADEL-->Setup-->Temperature) in the SPECTRE simulation to 100 degrees C and resimulate. Compare your simulation results.

Report Format: The report on this part of your lab should contain:

1. a title page (2%),

2. a list of all the cells you simulated (2%)

3. cell layout images (2%), without the load inverter.

4. the SPECTRE simulation inputs and outputs in the form of waveforms (16%),

5. a comparison of the smallest inverter at the different temperatures (4%), and

6. a discussion of cell rise and fall times and a comparison to the simulation results you got for Lab 1 (4%).

All these parts should be in a single lab report file in pdf format. Tar this lab report with the SPECTRE netlist for each layout cell (see note below), and the lab report and files from Part 2, described below. The report should be typed, not handwritten, and should be in pdf format. Reports submitted in .doc, .docx or other formats will not be graded.

Note: Netlist files can be obtained in the ADE L (simulator window) go to simulation--> netlist--> display.

Part 2: LATCH and FLIP-FLOP DESIGN 70%

To be posted next week. Layout simulations and other important information will be covered in the lab next week. See the following information and notes from Yilda for help with this lab.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. You will have two chances to upload your files. All files for Part 1 and Part 2 should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color except with permission of the instructors. Failure to follow these instructions could result in deduction of points.

LAB Hint: Do not name files or cells starting with a number - like 4inputnand. Cadence and/or SPECTRE might have trouble with this. They might also have trouble with names like /clk, so use notclk instead.

Notes from Yilda Irrizarry-Valle:

In case you are starting lab 2 during Spring break here are some comments:

1)      Running layout simulations is exactly the same as running schematic simulations (same steps, see the last page of Cadence Tutorial). The tutorial is on DEN-->Course Documents-->Cadence Tools.

2)      Few things are different:

a.       You should open the ADE L simulator window from the extracted view, not from the layout view (see the last page of Cadence tutorial).

b.      In stimulus input part you will need to setup the ground signal to 0 (dc voltage).  

c.       To plot the signals, you do it in the same way as for the schematic.

                                                               i.      The only difference is that you need to choose the signal (the metal or poly line) in the extracted view. 

                                                             ii.      You could also do it manually by using steps given in page 2 of the MeasurementCurrent.pdf file (the file you used in Lab1 for the measurement of current).   This file is also on DEN-->Course Documents-->Cadence Tools.

T

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