EE477 - s14 hw3

Homework Assignment #3

EE 477 Spring 2013 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 2/18/14

OR Ecopies due 5 PM 2/18/14 using the "Assignment" Function on DEN
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

Assume for the problems below that V_dd = 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

1. (10%) A PMOS transistor has Vs = 1.8 V , V_d = .9 V. Vg = .6 V. What region of operation is it in?

2. (10 %) An NMOS transistor has Vg = 1.8 V. V_d = .9 V. Is the transistor in the linear region of operation when Vgs =1.3 V?

3. a) (5 %) A PMOS transistor is used as a pass transistor (switch). The input voltage is Vin = 1.1 V. The gate voltage Vg=.4 V. The voltage Vout = 1.7 V at time t = 0. What is the final output voltage at t = infinity?

b) (3%) Does the PMOS transistor have body effect when t approaches infinity?

c) (10%) Assume the transistor width is 8 lambda and the length is twice minimum size. Compute the drain current flow I_{DS at t=0 and at t = infinity}.

4. a) (7 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = 1.1 V and Vout = .3 V. Vgn = 1.4 V, and Vgp = .4 V.

b) (8 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your answers.

5. (10%) Assume we have N NMOS transistors connected in series. If at t=0 the input voltage is Vdd and all internal nodes are 0 V (V1, V2,..., V_N), what is the maximum voltage at the output V_Nat t=infinity?

6. (10%) Find the voltages V₁, V₂, and V₃ at t=infinity. Assume that at t=0, V₁,V₂, and V₃ are equal to 0 V.

7. (5%) You might need to solve this problem after Thurs. lecture. What is the effective channel resistance of a 3 times width of a unit size PMOS transistor? Assume Vg=0.2V, Vs= 1.5V, Vd=1.4V.

8. (5%) What is the parasitic effect that is created when we have current flowing between Vdd and ground away from the transistor channels in a CMOS process? How can we avoid it?

9. (5%) Does the threshold increase or decrease if we use thick oxide instead of thin oxide under the poly in the gate region? Why?

10. (7%) Why is the substrate in NMOS connected to ground and in PMOS to Vdd?

11. (5%) Sketch the crossection of an PMOS transistor when Vds < Vgs-V_tp0. Show clearly the shape of the channel.

12. (10%) In an inverter, if Vin rises slowly, so there is a subthreshold current through the NMOS transistor whenVin<Vthn, will the NMOS transistor still move from cutoff to saturation when Vin=Vthn?