Homework Assignment #2

EE 477 Spring 2014 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 2/11/14

OR Ecopies due 5 PM 2/11/14 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

Turn in EITHER a hard copy or ecopy, not both.

1a. (35%) Design a 4-bit UP/DOWN counter with parallel load. The counter has unused states 0110 and 1100. The counter counts UP and DOWN in steps of 2. The current output should change when the clock rises. Include an asynchronous reset function. If reset is asserted asynchronously, the current number will become 0 and should stay zero until the next positive clock edge, even if reset is subsequently unasserted. New data is loaded into the flip flop only when reset is not asserted.

Each bit of storage should be a positive edge-triggered flip flop. Each flip flop should contain two latches, as described in class. The data loaded into the flip flop will depend on the data currently in the flip flop along with data in the other flip flops.

Design your counter at the gate level. Use transmission gates to build the multiplexers at the input to each latch.

Show your solution for the counter as a gate-level diagram.

1b. (5%) Compare the flip flop designed in part 1a. with a flip flop where the multiplexers at the input to each latch are designed with NAND gates. Which one is better? Why?

2a. (10%) Draw a gate level implementation of the function in Problem 5 of homework 1 using only NAND gates. Assume that complement inputs are available.

2b. (5%) Compare the cost of the designs in 2a. and Problem 5 of homework 1 in terms of the number of transistors.

3. (10%) Sketch the side view (slice down into silicon) of a stacked contact that connects poly to metal4 using colored pens or pencils.

4. (5%) List the steps needed to create the stacked contact that connects p+ diffusion to metal 3 using a positive photoresist process.

5.(5%) Sketch the crossection of an NMOS transistor when Vds> Vgs-Vt. Show clearly the shape of the channel.

6. (5%) Explain what a channel stop is.

7. (10%) In the figure below, draw the cross-section down into silicon along the horizontal yellow line.