Homework Assignment #1

EE 477 Spring 2014 Professor Parker

Hardcopies due in the course boxes in the basement of EEB 5 PM 2/3/14

OR Ecopies due 5 PM 2/4/14 using the "Assignment" Function on DEN


To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

1. (7%) Give the Boolean expression for a four-bit magnitude comparator computation with output

C

and inputs A (A0, A1, A2, A3) and B (B0, B1, B2, B3). A and B are being compared. C is high (1) when A is equal to B, and low (0) otherwise. A0 and B0 are the least significant bits respectively.

2. (8%) Show an implementation of the comparator computation in Problem 1 at the gate level using complementary NAND, NOR and INV gates. You may not use XOR or XNOR gates.

Note: You must invert inputs if you need the complements of the inputs in the circuit. You can use gates with any number of inputs.


3. (15%) Show an implementation of the four-bit maginitude comparator from Problem 2 at the circuit (transistor) level. You do not need to show the transistor level for identical gates. If you use 3 2-input NAND gates, you only need to show one of them.


4. (15%) Show the stick diagrams of each unique gate type you used in Problems 2 and 3, labeling the layers or using colors for the different layers as shown in lecture. If you have 3 2-input NAND gates, you only need to show one of them.


5. (15%) Draw a transistor (circuit) level diagram for a compound gate that implements the following Boolean function

H = /[XZ(Y+W) +/P(Q+ST)U + (N+R)(M+LOK)]

without simplifying the Boolean function.

You can assume that all inputs as well as their complementary inputs are available. Label the sources and drains of all the transistors.


6. (10%) Show a design at the transistor level that implements the following Boolean function. Use only transmission gates. You can assume that all inputs as well as their complementary inputs are available


Y= /C(A XOR B)+C(A XNOR B)


7. (10%) Asssume you have a transmission gate where the control signals X and /X are the inputs to the nmos and pmos gates, respectively. What would the problem be if X and /X do not arrive at the same time?


8. (10%) Design a latch at the gate and transistor level that has two possible data inputs (D0 and D1) plus the feedback path (Q). The latch should load when clock is high. The latch can be asynchronously set. Set means the output of the latch that is fed back to the mux, Q, is high. The 3-input MUX used in the latch should be constructed using transmission gates. Please clearly mark the inputs (D0, and D1), controls (select and set ), clock and outputs (Q and ~Q) on the circuit diagram.


9. (5%) Make a directory (folder) on your UNIX account that is called HW1. Create a small file on your UNIX account that contains your full name on the first line and your student number on the second line. Use EMACS or any other unix editor to create the file. Save the file in the HW1 directory as yourlastname.txt. Change the directory to HW1. Give the results of typing the command ls -l yourlastn* , leaving off the last three letters of your last name. You can provide a print screen or just copy / paste the text. If your last name is two words with a space in between, use the last word.


10. (5%) Sketch the crossectional view of p-channel mosfet.