University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 (worth 20% of final grade)

Module Design, Cadence and SPECTRE

Due 5/6/13 4:59 PM

There will be no extensions so plan your time accordingly!

This lab addresses the design of a special-purpose circuit. The circuit contains a simplified digital neuron that fans out to 24 other neurons. There are two parts to the lab: The neuron and the entire neural network. Be sure to finish and test your schematic of the neuron before you start the neuron layout. As you are laying out the neuron, plan how you are going to fit all the neurons together. Note the rules given below.

Rules:

  1. You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have to design circuits to generate the other clocks.
  2. /load is not an input to the circuit. You need to generate it if you need it.
  3. You must use the cells you designed in labs 1 and 2 to build your neuron and your neural network. Do not change the circuit structure of your cells unless your cells do not meet the requirements of lab 1 or 2 (i.e. you lost points). You can rearrange the layout slightly or resize transistors as needed. Do not change the methodology by rotating transistors, rearranging transistors, connecting inside the cell on different layers, or changing your interconnection strategy (for example, you might decide that all inputs come in the top of the cell, so you can't change that). You can move ntaps and ptaps around.
  4. You must have ntaps and ptaps according to the rules.
  5. You can tune the circuits by changing transistor sizes as needed or to squeeze out empty space.
  6. You cannot remove unused inputs or unused logic from your cells.
  7. Make sure your ohmic contacts (ntaps and ptaps) meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course the taps should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts, as Cadence will do for you automatically.
  8. You can use metal layers 1-4 for the neuron, and layers 1-6 for the network.
  9. All signals should use the names we have given below.
  10. You need to generate all inverted inputs, including /clock.
  11. On your layout, all inputs and outputs to the circuit must be routed to the edges of the layout and must be labeled.

The Neuron and Neural Network Laboratory Goal

You will produce a working schematic and layout for the neuron. You will use the simulated neural network to adjust your timing (clock period) to be as short as possible. For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product of the entire neural network. Final project designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com.

The Digital Neuron

There are 10 inputs to the neuron:

  • 6 single-bit data inputs to the neuron, T, U, V, W, Y, Z that could be different every clock cycle
  • a single-bit inhibitory input I,
  • Load control signal, that allows the output ff to be loaded with a new value,
  • Reset control signal
  • and a clock with 50% duty cycle.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

  • Each data input and control input has a single bit.
  • The inhibitory input I is a single bit.

  • The neuron output contains a firing flip-flop you designed in Lab 2, and the output of the flip-flop AP represents the output of the neuron.
  • The neuron "fires" when the Boolean expression (VY+WY+VZ+WZ+YZ+VW) + (/I)[T + U] evaluates to a 1.
  • After the negative edge of the clock, if the neuron fires, the output of the firing flip-flop goes from low to high. The output remains high until the next falling clock, when it is lowered if the inputs do not cause a "1" to be loaded into the FF.
  • Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
  • Note that you might find a way to use the compound gate you designed in Lab 1, and you might need more than one of these gates.

A block diagram of the neuron is shown below.