EE477 - s13 lab2

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #2

Latch/FF Design, Layout and SPECTRE Simulations

Due April 13, 2013, 4:59 PM

V_dd = 1.8 v.

A note about well and substrate contacts (ntap and ptap): Make sure your ohmic contacts meet the following requirement:

* Every cell should have a well and substrate contact.

* For larger cells, include at least two contacts per 50x50 lambda square, one for the p-substrate and the other for the n-well, assuming there are both NMOS and PMOS transistors in the space.

* Every separate block of n-well should have at least one ohmic contact.

* For all your contacts, you will get the best design if you use multiple minimum-size contacts for large contact areas and not large contacts. Cadence will do this automatically for you if you try to use large contacts.

Part 1: Lab 1 Cell Layout SPECTRE Simulations 30%

A. Simulate the cell layouts you designed in Lab 1 using SPECTRE (inverters, NANDs, transmission gate and compound gate),

* Your device sizes should be the same as you were instructed to attain in Lab 1. Do not adjust rise and fall times by changing transistor sizes here.

* Attach the smallest inverter cell layout as a "load" to the output of each cell. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell. Read the simulation output from the cell you are testing, not the load inverter.

* Insure when you create extracted view from the layout that you include all parasitic capacitances.

* For the simulation use the same inputs in the same order as you did for the schematic simulations, including your worst-case simulations.

* Use a rise and fall time for the inputs signals of .1 ns.

* Note the rise and fall times at the outputs of each cell.

B. Change the temperature of the smallest inverter layout (go to ADEL-->Setup-->Temperature) in the SPECTRE simulation to 100 degrees C and resimulate. Compare your simulation results.

Report Format: The report on this part of your lab should contain:

1. a title page (2%),

2. a list of all the cells you simulated (2%),

3. layout images (2%),

4. the SPECTRE simulation inputs and outputs in the form of waveforms (16%),

5. a comparison of the smallest inverter at the different temperatures (4%), and

6. a discussion of cell rise and fall times and a comparison to the simulation results you got for Lab 1 (4%).

All these parts should be in a single lab report file in pdf format. Tar this lab report with the SPECTRE netlist, and the lab report and files from Part 2, described below. The report should be typed, not handwritten, and should be in pdf format. Reports submitted in .doc, .docx or other formats will not be graded.

Part 2: LATCH and FLIP-FLOP DESIGN 70%

A. Use only the cells you have already constructed to design a latch, and use two latches to build a CMOS D flip-flop schematic in Cadence. Design the two latches as separate cells and then place them together to form the flip-flop. You can use one of the larger inverters one or more places in the flip flop if it gives you a faster design. You can assume that the flop-flop output will terminate in a load inverter just like you used in Lab 1.

Assume the flip-flop is clocked and can be synchronously reset.

clock, /clock, Data D, synchronous reset, synchronous load and synchronous /load are inputs to your design.

Load is active high.

When Load is low, the data will recirculate, regardless of the clock.

The flip-flop should be negative edge triggered.

The clock signal should not be gated (in other words, the clock signal should not pass through any logic gates before arriving at the flip-flop).

The transistors in the gates used in the flip-flop should be sized as they were sized for Lab 1. Do not use ratioed (pseudoNMOS) logic. Do not use dynamic logic or dynamic storage (not covered yet).

B. Simulate the flip-flop schematic you built in Cadence using SPECTRE, assuming the data D, clock, /clock, reset, load and /load signals are inputs to your design. Be sure to try all possible combinations of data inputs versus present state of the flip flop, including the waveforms shown below. Be sure you test reset. Start with clock low, D low and load high. For the simulations, attach your inverter schematic as a "load" to the flip-flop output. To do this, create a new cell that contains the cell you are testing and also the load (inverter) cell.

Adjust the timing of your clock to be as fast as possible and still have the circuit work properly. Make sure the inputs have settled a setup time before the clock edge. The waveforms shown below show the order of changes of inputs you are to use for the simulations. You might have to set initial conditions in the latch to get SPECTRE to converge. This will be explained in the discussions. Proper functioning includes having the low output be less than .1 Vdd and the high output being greater than .9 Vdd.

The clock and all input signals should have a rise and fall time of .1 ns.

C. Use the same layout methodology you used in Lab #1 to layout the flip flop, using only the bottom three layers of metal, metal 1, metal 2 and metal 3.

D. Create SPECTRE (simulation netlist) files for the flip-flop layout from Cadence and simulate with V_in (Data) changing from 0 v. to Vdd (1.8 v.) and then Vdd to 0 v. For the simulations,

attach your inverter cell layout as a "load" to the flip-flop output. Do not copy paste the inverter layout but use the inverter layout as an instance.

Again assume the data D, reset, clock, /clock, load and /load signals are inputs to your circuit.

Proper functioning includes having the low output be less than .1 V_dd and the high output being greater than .9 V_dd.

The clock and all input signals should have a rise and fall time of .1 ns. Plot V_in (D) and V_out (Q) versus time.

Note the delay between V_in changing and V_out(Q) changing. Use the definitions of delay given in the text as the time between the input achieving 50% of its final value and the output achieving 50% of its final value. This will give us the sum of the setup and clock-to-Q times, with setup the time before the clock, and clock-to-Q the time after the clock.

The clock should have a 50% duty cycle. Make the clock as fast as you can and still get correct results. Estimate the contamination delay for the circuit (fastest data propagation path from the output of the FF to the input of any FF).

What to turn in for Part 2: Your Lab 2 part 2 (in pdf format) should contain the following items:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number (2%).
A description of the flip-flop you built, including a transistor-level or gate-level circuit diagram printed from Cadence (18%).
The latches and flip-flop layout screen captures. Make sure to show the pin names (15%).
A description of all the simulation experiments you ran with SPECTRE (5%)
SPECTRE input waveforms and outputs for the flip-flop schematic and layout as shown in waveforms for all the simulation experiments. Put your input and output waveforms onto multiple graphs so we can read them more easily (30%). Include a statement of contamination delay and fastest clock for the schematic and layout. Show all the simulation waveforms you ran to measure any timing quantities (clock period, for example).

Items 1-5 should all be in a single report. Tar this report along with the SPECTRE input netlists - these should not appear in the report, but be submitted as separate files, tarred with the reports and the items from part 1 of this lab, and upload to the assignments page of the blackboard. Do not put the SPECTRE input or output text files into the report itself. We need to be able to execute the input files.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. You will have two chances to upload your files. All files for Part 1 and Part 2 should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color except with permission of the instructors. Failure to follow these instructions could result in deduction of points.

LAB Hint: Do not name files or cells starting with a number - like 4inputnand. Cadence and/or SPECTRE might have trouble with this. They might also have trouble with names like /clk, so use notclk instead.