University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #1

Logic Gate Design/Layout and Simulation Experiments

with Combinational Cells

Due 3/14/13, 5:00 PM Via the DEN Blackboard Assignment Function (worth 10% of final grade)

YOU MUST WORK INDEPENDENTLY ON THE LABS: THERE ARE NO PROJECT GROUPS

1. (27%) Use CADENCE Virtuoso schematic capture to design complementary CMOS logic gates at the transistor circuit level for the following functions:

  1. 3 inverters,
  2. transmission gate,
  3. 2-input NAND,
  4. 4-input NAND, and
  5. a compound gate that implements the function COMPOUT = NOT {A[B+C+D]}.

Size your transistors as discussed below.

Transistor Sizes:

Your lab technology lambda is 100 nm. Assume Vdd = 1.8v. For your schematic and layout you must make the transistor dimensions in multiples of .5 lambda.

Start your device sizing by experimentally determining a value for transistor beta ratio for the inverter.

The Basic Inverter #1: The NMOS transistor in the inverter should be "unit" transistor sized, as defined in the text and lectures, paying attention to the current design rules in the lab. For the inverter, widen the PMOS transistor channel as required so that the rise time and fall time are within 10% of each other.

The Larger Inverter #2: Size both the transistors in this inverter 4 times as wide as in the basic inverter.

The Largest Inverter #3: Size both the transistors in this inverter 4 times as wide as in inverter #2.

Remember that you can put two or more unit-sized transistors in parallel in place of widening a single transistor if it helps keep your methodology consistent.

The Transmission gates: Size the transistors the same as the inverter #2 transistors.

The NAND gates: For the 2-input and 4-input NAND gates, use unit size NMOS transistors and make the PMOS transistors wide enough to have rise and fall times within 25% of each other.

The compound gate: For the compound gate, experiment with transistor widths that give output rise and fall times within 25% of each other, in the worst case. Note that the sequence of inputs that give worst-case timing might be different from the required input sequences specified below. Note also that when you have adjusted the critical path, other paths may need adjustment as well. Worst-case timing and critical paths will be discussed in class. You can manipulate the Boolean equation as desired. Include your choice of worst-case path in your discussion.

2. (20%) Simulate your transistor circuits (Cadence circuits) using SPECTRE to determine that they function properly.

* Label your inputs A, B, C and so on. For example, the 2-input gates have inputs A and B. Label your outputs INV1OUT, NAND2OUT, etc.

Attach your inverter #1 design to the output of each gate (including the inverter) prior to circuit extraction and simulation to provide a load capacitance. The output you should plot is the input to this load inverter.


* Simulation timing: Assume .1ns rise and fall time for your inputs. Hold all input values stable for at least 1.8ns.


* Show simulations of each gate with all possible combinations of inputs.


* Change the inputs in the following manner:

4-input NAND: ABCD = 0000, ABCD = 0001, ABCD = 0010....etc.


2-input NAND: For the 2-input gates AB = 00, AB = 01, etc.


Compound gate: For the compound gate, simulate all combinations of A, B, C and D, from 0000 to 1111. Please change the inputs in the order given so that we can grade what you are doing easily.



* For the 3 inverters only: Measure average current in your inverters and multiply by Vdd to obtain average power. Measure over the period from .1ns before the input falls to .1ns after the input becomes low. There is a measure method given in the tutorial we posted. Note that you need to use a load inverter so use the smallest one as with other simulations.


* For the smallest inverter increase the input voltage starting at 0.0v until the slope of the input/output transfer curve = -1. Then find the low noise margin, assuming VOLMAX = 0.0v. Find the high noise margin in a similar way.

3. (30%) Layout your cells with Cadence (each circuit layout is a "cell"). Use the TSMC technology (NCSU_TechLib_tsmc02) as instructed in lab. Put at least one ntap and ptap (ohmic contacts) in each cell. If you have multiple n-wells in a cell, each needs an ohmic contact.

Required Layout Design Methodology:

Design all of your cell layouts so that they can be placed next to each other either vertically or horizontally without having layers connect that should not.

Use a uniform methodology to design all the gates, and only use metal1 and metal 2 for interconnect.

Make sure that you minimize the use of poly (for example, you could only use poly around the gate region of each transistor).

Your goal is to insure that it is easy to build more complex designs out of your gates, and to keep the cells small, with few layer changes for each connection.

You want to extend your methodology to design compound gates as well.

Keep in mind as you design the inverter that you may want to redesign it later with wider transistors.

At this point in the semester, try to minimize the white space to create cells that are as small as possible, but easily combined into larger circuits. One hint: you could design the cells so that the output of each cell lines up exactly with an input of every cell type. The output and input can line up horizontally or vertically.

The following is one example of such a methodology:

"Design each cell to be the same height. Power and ground will be routed horizontally later, and the input to each cell should be vertical. The output should come out horizontally on the metal 2 layer. Use a style similar to the cells shown in Fig. 1.10 of the text."

This is only an example. Instead, you might choose to design each cell to be the same width, for example. You might route the inputs to the cell horizontally, and use different layer assignments than the example.

4. (5%) Use LVS to verify that your cell layouts are identical to the schematics. You will simulate the layouts with SPECTRE in Lab 2.

5. (10%) Layout a small logic block that implements the function COMPOUT = NOT {A[B+C+D]} (the same function as the compound gate).

using your inverter #1 and/OR NAND gate cells from Part 3. This exercise should help you tune your cells so that they can be connected easily into logic blocks for the final project. Be sure that inputs/outputs with the same name are connected on the layout. Do not be concerned with simulation or device sizing.

6. (8%) Submit your lab writeup. The lab writeup is worth 8% of the Lab 1 grade.

Turn in final transistor-level schematics, layouts and schematic SPECTRE simulation outputs for all cells. Turn in the layout for the logic block. You do not need to simulate this block.

Lab Report Contents:

  1. Title page
  2. Discussion and explanation of how you sized transistors, and the beta ratio you found, including measured rise and fall times.
  3. Description of your design methodology.
  4. Transistor schematics of gates.
  5. Layouts of gates, captured as images, making sure the images are high enough resolution so the grader can see layout details and inputs/outputs are labeled.
  6. SPECTRE outputs for each gate schematic simulation in the form of images showing the waveforms.
  7. Table showing cell sizes for all the cell designs
  8. Layout of the logic block, captured as an image.
  9. Conclusions about the lab, especially about sizing the transistors in the compound gate.

Your lab report should be a pdf file. Please do not submit a .doc or .docx file. Name the report as follows: LastnameLab3.pdf


Include as separate files:Each file called si.out generated in a folder called LVS showing the results either match or mis-match for each cell layout. Be sure you rename the si.out file after each cell is verified to something like NAND2.out. Otherwise it will get overwritten.

Use the "tar function" on UNIX to put all the files including the report into a single file. (See wikipedia for instructions on how to tar a file). Do not put into rar format. Students submitting multiple files will lose points. Your reports must be in pdf format.


Instructions on how to print your layout and waveform images in color:


For layouts:


In the layout editing window:

File->Print

"Submit Plot" window will pop up.

You can choose plot with "header" or "notes" or disabled both

Click on Plot Options

"Plot Options" window will pop up.

‧ Display type: display

‧ Plotter Name: (change to) Generic 300 dpi Adobe Post Script Level 2 Plotter (for color images)

‧ Send Plot Only To File : (type in file name ending with .ps)


Then use distill function to convert .ps to .pdf


The same instruction can be used to print the schematic.


Here is the instruction to print waveforms from Cadence:


File->Save as Image

>> Then enter a name and save in PNG format.


It might take several minutes so be patient. The hourglass should appear.



Submit the assignment using the Assignments function on the DEN blackboard.

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Some Guidance from the TAs:


Cadence is case sensitive. Case sensitive means that the labels in your schematic should be consistent with the labels in your layout. For example, if in my schematic I use A for the input of the inverter then in the layout I should use A for the input of the layout inverter (If I use a instead of A it won’t work).


The label for the power supply terminal in the layout should be vdd! (do not use Vdd!), for ground use gnd! (do not use Gnd!)


************ Rise/Fall time

There is an option in the rise time window that allows you to measure all the rise times in a simulation. It is the # of occurrences. The default is “single”, you can change it.


************Transmission gate

It is necessary to put on the schematic a floating vdd and a floating gnd in order to compare the LVS because you have them in your layout (vdd!, gnd!).


*********** Flipping layouts:

In case you need to flip the layout cells you can do the following: select the cell--> right click-->move and then select the rotate option of your preference.


****** A final comment

If the layout/schematic does not match, please verify all the pins and all the connections on each node. Also, please remember to put ntap and ptap on the layout. If you couldn't find the errors, then I suggest to repeat the layout again, though 99.9% of the time the LVS error is due to a wrong connection or wrong pin labels. These cells are small enough to be able to find the error. You can use the help of the LVS output file to identify the error.


Before sending the TAs emails please try all the possible options and verify all possible layout/schematic errors.


Good luck!