EE477 - s13 hw6

Homework Assignment #6

EE477 Spring 2013 Professor Parker

Hardcopies due in the course boxes on the third floor of EEB 5 PM 4/15/13

Ecopies due 5 PM 4/15/13 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

Assume for the problems below (unless otherwise stated in the problem) that

V_dd= 1.8 V, V_tp = - 0.4 V, V_tn = 0.4 V, V_tp,BE = - 0.5 V, and V_tn,BE = 0.5 V.

T_ox= 41 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = 0.1 micron.

C_jbsn = 9.725 x 10^-4 pF/ μm² and C_jbswn = 2.27 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

C_jbsp = 11.57 x 10^-4pF/ μm² and C_jbswp = 1.8 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

x_j (diffusion depth) = 0.1 microns.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V

Assume lambda is .1 microns. Metal thickness is .5 microns.

1) a) (10%) Compute the worst-case falling RC time constant at the output of the compound gate in Homework Assignment #5 of Spring 2013 using a lumped model, in terms of R_chn, C_dpand C_dn. Assume the original gate, not one you modified to contain Euler paths. Assume all transistors are unit size.

(b) (10%) Compute the worst-case falling RC time constant at the output using an Elmore delay model, in terms of the variables given above.

2) a) (15%) Connect an output of a 3-input NOR gate through two long wires to a 2-input NAND gate on one branch, and a transmission gate and inverter on the other branch. A sketch of this circuit is shown below. Assume the transmission gate is on, and the wire length between the transmission gate and inverter is negligible. For all gates, assume R_chn = 1000 ohms and R_chp = 4000 ohms, C_gn=C_gp=C_dn=C_dp= 10 fF. For the wire assume R_w = 10 ohms and C^w = 6ff. Compare the rise and fall times at the input to the transmission gate using the Elmore delay model. Use π-model for the long wires.

b) (10%) Insert a pair of inverters 1/3 and 2/3 of the way along both of the wires from the NOR gate to the NAND gate and to the transmission gate. Compare the fall time constant at the input of the transmission gate to the fall time constant at the input of the inverter inserted 1/3 of the way along the long wires. Use the Elmore delay model. Also compare to the results of Part (a). Again use the π-model for the wires.

3) (10%) Assume a combination of flip-flops as shown below. The combinational logic used is an inverter. The flip-flops used are negative-edge triggered like the one you are building in Lab 2, but they do not have the load and reset functionalities. The timing diagrams for the flip-flops and inverter are shown below. Assume we want a set-up time of 200ps to accommodate an early clock signal. What is the minimum clock period that can be used for this configuration?

4) (15%) Use a chain of inverters to drive a 1pF load. How many stages (n) are required in the inverter chain, assuming the first stage is an inverter with unit transistors, assuming equal delay in all stages, and assuming C_g(n+p) for the first inverter in the chain = 8 fF? You can assume C_d(source or drain) = 3*C_gn = 3*C_gp. How much wider (a) are the transistors in each stage than the previous stage?

5) (10%). For the screening example covered in class on April 4, assume that you insert both additional inverters at the beginning of the long wire, right at the output of the original inverter, making the two additional inverters into a superbuffer with transistors 4.5 and 20 x wider than the original inverter. Use the RC time constant method (lumped) to determine whether the super buffer speeds up the circuit.

The original circuit is as follows: An inverter drives a capacitive load. The inverter drives a wire that is 120 microns in length. The wire has a capacitance of 0.5fF/micron. There are 12 NAND gates, spaced every 10 microns along the wire, that have a total gate capacitance of 10fF for both NMOS and PMOS transistors. The diffusion capacitance of the driving inverter that affects rise and fall time is a total of 10fF for both NMOS and PMOS transistors.

Your manager tells you that you have room for up to two additional inverters of the same size to add to the circuit.

6) (5%). Assume a wire has a resistance and capacitance R/micron = .056 ohms, and C/micron = 50 fF. The delay of the wire was measured to be 529 ps. What is the length of this wire?

7) (10 %) For the network of gates shown on page 20-8 of Lecture 20, replace each NAND gate with a NOR gate. Assume C_d = C_g. Assume Gate 4 drives a load capacitance of 2C_g. Assume the transistors are unit size. Compute the total longest delay through the network starting with the fall time at the output of Gates 1 and 5.

8) (5 %) Assume we have a wire with dimensions w/l = 0.8, w/h = 1, and t/h = 1. What is the fringing field factor?