EE477 - s13 hw5

Homework Assignment #5

EE477 Spring 2013 Professor Parker

Hardcopies due in the course boxes on the third floor of EEB 5 PM 4/5/13

Ecopies due 5 PM 4/5/13 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

Assume for the problems below that

V_dd= 1.8 V, V_tp = - 0.4 V, V_tn = 0.4 V, V_tp,BE = - 0.5 V, and V_tn,BE = 0.5 V.

T_ox= 41 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = 0.1 micron.

C_jbsn = 9.725 x 10^-4 pF/ μm² and C_jbswn = 2.27 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

C_jbsp = 11.57 x 10^-4pF/ μm² and C_jbswp = 1.8 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

x_j (diffusion depth) = 0.1 microns.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

^{1. (15%) Use the compound gate shown below. Label the sources and drains of all transistors. Show an identical Euler path for both NMOS and PMOS transistors by listing transistor inputs on both paths. If you cannot find a complete Euler path, you might need to add an extra transistor or two. Do not rearrange the transistors.}

^{2. (20%) Give a stick diagram for the compound gate in Problem 1 above, using the Euler path you found.}

^{3. (10%) Size the devices in the longest paths in the compound gate to give equal rise and fall times in the worst case.}

^{4. (10%)}How many diffusion capacitances get charged/discharged in the worst case that affects the output node, assuming no diffusion regions are shared?

^{5. (15%) A design has a number of common inputs/outputs that need to be connected. Use the left edge algorithm to connect common inputs using as few tracks as possible. The starting and ending positions of each common input are given below. You can assume the inputs come from either the top or the bottom of the channel to make the problem easier. If two wires start or end at the same point that does NOT mean they are or should be connected.}

^{A (2,9)}

^{B (1,5)}

^{C (1,3)}

^{D (5,11)}

^{E (6,8)}

^{F (11,14)}

^{G (4,8)}

^{H (10,15)}

^{I (9,13)}

^{6. a)(10%) Compute the gate capacitance of an NMOS transistor in linear region that is twice minimum length and twice minimum width.}

^{b) (5%) Compute the estimated gate capacitance in the saturation region.}

^{7. (10%) Compute the drain diffusion capacitance of a PMOS transistor with diffusion length 10 lambda and width 3 lambda. The shape of the diffusion is illustrated in the figure below. The channel is on the left of the diffusion.}

8. (5%) Compute the resistance of poly used as interconnect shown in the figure below. The sheet resistance Rs = 4.1 ohms per square.