Homework Assignment #3

EE 477 Spring 2013 Professor Parker

Hardcopies due in the course boxes on the third floor of EEB 5 PM 2/18/13

Ecopies due 11:59 PM 2/18/13 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

Assume for the problems below that V_dd = 1.8 V, V_tp0 is -.7 V. and V_tn0 is .7 V. V_tpbodyeffect is -.9 V. and V_tnbodyeffect is .9 V.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

1. (10%) A PMOS transistor has Vs = 1.5 V , Vd = .9 V. Vg = .2 V. What region of operation is it in?

2. (10 %) An NMOS transistor has Vgd = .9 V. Vs = .3 V. Is the transistor in the linear region of operation when Vg =1.2 V?

3. a) (5 %) A PMOS transistor is used as a pass transistor. The input voltage is Vin = .8 V. The gate voltage Vg=.3 V. The voltage Vout = 1.8 V at time t = 0. What is the final output voltage at t = infinity?

b) (3%) Does the PMOS transistor have body effect when t approaches infinity?

4. a) (7 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = 1.3 V and Vout = .2 V. Vgn = 1.2 V, and Vgp = .4 V.

b) (10 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your answers.

5. (10%) Compute the drain current flow I_DS in a PMOS transistor when Vd = .9 V, Vs = 2 V, and Vg = .5 V. Assume the transistor width is 16 lambda and the length is 2 lambda.

6. (5%) What is the effective channel resistance of a unit size NMOS transistor?

7. (10%) What happens to threshold voltage if transistor source and body are not at the same voltage?

8. (5%) Indicate one advantage and one disadvantage of using polysilicon for the gate of transistors.

9. (5%) How can we prevent latchup to occur?

10. (10%) Why do we use thin oxide under the gate region, while outside the active area thick oxide is used?

11. (10%) What can we do to avoid mask misalignment problems?