Homework Assignment #2

EE 477 Spring 2013 Professor Parker

Hardcopies due in the course boxes on the third floor of EEB 5 PM 2/11/13

E copies due 5 PM 2/11/13 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.

1. (35%) Design a binary counter that counts down from 24, 3 at a time. The output sequence is 24, 21, 18, …, 3, 0, and then it repeats itself. The current output should change when the clock rises. Include a synchronous reset function. The output resets to 24 when reset is asserted. The counter is reset when the clock rises. New data is loaded into the flip flop only when reset is not asserted.

Each bit of storage should be a positive edge-triggered flip flop. Each flip flop should contain two latches, as described in class. The data loaded into the flip flop will depend on the data currently in the flip flop along with data in the other flip flops.

Design your counter at the gate level. Use NAND gates to build the multiplexers at the input to each latch.

Show your solution for the counter as a gate-level diagram.

2. (15%) Draw a transistor (circuit) level diagram for a compound gate that implements the following Boolean function:

Z = (A+/B)C + DE + /[/F+/G(H+I+J)K + /L/MN]

You can assume that all inputs as well as their complementary inputs are available. Label the sources and drains of all transistors.

3. (10%) Sketch the side view (slice down into silicon) of a stacked contact that connects n+ diffusion to metal4 using colored pens or pencils.

4. (10%) List the steps needed to create the stacked contact in Problem 3 using a negative photoresist process.

5. (5%) What is the importance of depositing poly before diffusion when fabricating transistors?

6. (5%) When sizing transistors, which dimension (length or width) is adjusted? Why is this dimension adjusted and not the other one?

7. (15%) In the figure below, draw the cross-section down into silicon along the vertical yellow line.