Homework Assignment #1

EE 477 Spring 2013 Professor Parker

Hardcopies due in the course boxes on the third floor of EEB 5 PM 2/4/13

Ecopies due 5 PM 2/4/13 using the "Assignment" Function on DEN

To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work. Turn in EITHER a hard copy or ecopy, not both.

1.You are building a subtractor. This problem focuses on a circuit that generates the subtraction of 3-bit unsigned numbers X (x₃,x₂, x₁) and Y(y₃, y₂, y₁ ); x₁ and y₁ are the least significant bits respectively. You are not allowed to use 2's complement operation to perform the subtraction.

a) (5%) Give a truth table for a full subtractor. The inputs of the full subtractor are Xi, Yi and Bi-1 (borrow in) and two outputs Di (the result) and Bi (borrow out).

b) (5%) Draw a timing diagram that illustrates the full subtractor operation.

c) (10%) Give the Boolean expression for the final "borrow out" function in terms of the 2 numbers: X (x₃,x₂, x₁) and Y (y₃, y₂, y₁ ).

2.(15%) Show an implementation at the gate level using complementary NAND, NOR and INV gates of a circuit that generates the "borrow out" function found in problem 1c). Note: You must invert inputs if you need the complements of the inputs in the circuit. You can use gates with any number of inputs.

4.(5%) Show the CMOS circuit for the NAND, NOR and inverter gates used in your design in Problem 2. Identify the drain and source terminals.

5.(15%) Show a compound gate implementation for F, given that its function is

F = [{A*/B*/C+ B*/A*/(C+D) + /A*/B}*{/(A+B)*(E+G)*H}]. “/” indicates complement. Note that all compound gates result in a complemented output so you will have to arrange the equation in the form

F = /{Boolean function} to implement it as a compound gate. Assume the complements of the inputs are available.

6.(10%) Show a design at the transistor level implementation for the following function S=A

B

C . Use only 2-1 Muxes implemented with transmission gates. Assume the complements of the inputs are available.

7.(10%) Design a latch at the transistor level that has two possible data inputs (D₀ and D₁) plus the feedback path (Q). The latch should load when clock is high. The latch can be synchronously Reset when clock is high and asynchronously Set. Reset means the output of the latch that is fed back to the mux, Q, is low. Set means the output of the latch that is fed back to the mux, Q, is high. The MUX used in the latch should be constructed using transmission gates. Please clearly mark the inputs (D₀, and D₁), controls (select, /select, Reset, Set), clock and /clock, the outputs (Q and ~Q) on the circuit diagram. “/” indicates complement

8.(15%)Show the stick diagram for a 5-input NAND gate, labeling the layers or using colors for the different layers as shown in lecture.

9. (10%) In the mux you have designed in problem 6, what are the circumstances when more than one input can get transferred to the output at the same time? If we wait long enough after the inputs and control signals have changed, will we get the correct result at the output?