EE477 - s12 lab3

University of Southern California

Department of Electrical Engineering - Systems

EE 477 Laboratory #3 (worth 20% of final grade)

Module Design, Cadence and SPECTRE

Due 5/1/12 11:59 PM

There will be no extensions so plan your time accordingly!

This lab addresses the design of a special-purpose circuit. The circuit is a simplified digital neuron. There are two parts to the lab: The schematic of the neuron and the layout. Be sure to finish and test your schematic before you start the layout. Note the rules given below.

The digital neuron

There are five inputs to the neuron:

a data input to the neuron, D, that could be different every clock cycle
a single-bit inhibitory input I,
Load control signal, that allows the output ff to be loaded with a new value,
Reset
and a clock with 50% duty cycle.

Name your signals as shown in bold above. The output should be named AP. It is important you follow this naming convention so we can verify that your circuit works.

The basic Neuron Function:

Each data input and control input has a single bit.
The inhibitory input I is a single bit.
You need to generate all inverted inputs, including /clock.
The neuron output contains a firing flip-flop you designed in Lab 2, and the output of the flip-flop AP represents the output of the neuron.
The neuron also contains sequential circuitry that "remembers" the past 4 inputs in some manner.
The neuron "fires," as long as I is held high, when the D input is high, and 2 of the last 4 D inputs are high. The conditions for firing (loading a "1" into the FF) are recomputed every clock cycle. The inhibitory input I basically prevents the neuron from "firing" when it is asserted low. So as long as I is high, the neuron can fire if input conditions hold. You need a total of 3 "1"s on the D input, including the present input, for the neuron to fire.
After the negative edge of the clock, if the neuron fires, the output of the firing flip-flop goes from low to high. The output remains high until the next falling clock, when it is lowered if the inputs do not cause a "1" to be loaded into the FF.
Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance.
Note that you might find a way to use the compound gate you designed in Lab 1, and you might need more than one of these gates.

A block diagram of the neuron is shown below. I have removed the feedback from the AP output but you can still use it if you like.

Neuron input/output list:

D - 1 bit
I - 1 bit
Load - 1 bit
Clock - 1 bit
Reset - 1 bit
AP (output ff) - 1 bit

Rules:

You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have to design circuits to generate the other clocks.
/load is not an input to the circuit. You need to generate it if you need it.
You must use the cells you designed in labs 1 and 2 to build your neuron and your circuit. Do not change the circuit structure of your cells unless your cells do not meet the requirements of lab 1 (i.e. you lost points). You can rearrange the layout slightly or resize transistors as needed.
You must have ntaps and ptaps according to the rules.
You can tune the circuits by changing transistor sizes as needed.
You cannot remove unused inputs or unused logic from your cells.
On your layout, all inputs and outputs to the circuit must be routed to the edges of the layout and must be labeled.

The Neuron Laboratory Goal

You will produce a working schematic and layout for the neuron.

Layout Instructions for The Neuron:

1. Make sure your ohmic contacts (ntaps and ptaps) meet the following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course the taps should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50x50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts, as Cadence will do for you automatically.

2. You can use metal layers 1-6 for the neuron.

3. For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product of the entire neural network. Final project designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design.

4. Use LVS to verify your layout prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected.

The Laboratory Steps:

1. Design your neuron circuit and create a Cadence circuit (schematic) diagram using the circuits/cells you have already designed in Labs 1 and 2. You cannot design new cells for Lab 3. Include your logic/gate level diagram for your neuron. Designing the circuit that "remembers" the past inputs will take some time and planning.

2. Simulate your neuron schematic with SPECTRE to ensure that your design works correctly.

Use the following sequence of inputs for initial testing:

a) Set load to 0 and keep it low. All other inputs should be 0. Reset your neuron flip flop.

b) Set load to 1and keep it high. Then test your neuron by sequencing through all combinations of inputs starting with D = 0, then 1, then 0, alternating for 6 inputs. Only the final output should be high according to the conditions given above.

c) Now set I = 0 (inhibition) and sequence through the same inputs: 0 and 1 alternating. The output AP should be low at all times.

d) Reset the neuron flip flop. Now set load to 0 (zero). Set a string of 5 inputs to 11111, and I = 1. The flipflop output should remain zero.

3. Design and simulate your neuron layout with SPECTRE using the same sequence of inputs as in Step 2. You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

Testing Strategy

Here is a testing strategy that might be useful to you: Design the schematic first and test. Then design the layout and test each part as you build it.

Design and test at each stage. Design the output flip-flop first. Then design the logic and the output of the logic that makes the neuron fire if the logic creates a "fire" situation. Test the logic separately first. Then add the flip-flops. Then test the entire neuron

Here is a sample timing diagram for the neuron.

~~A sample timing diagram for the neuron will be posted in a couple of days.~~

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. There will be two prizes, one for the best undergraduate design and one for the best graduate design. Pay close attention to the specific delay you are to measure.

The delay you should measure with SPECTRE is the clock cycle or clock period. However, of course, your outputs should appear during the cycle shown in the timing diagram. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock cycle. If you compute the area-delay product wrong, or you do not compute it you will lose points.

Upload your report to the assignments function of Blackboard, including your layout and simulation files as a TAR file just like you did in lab 2 so that we can test (simulate) your circuit to be sure it performs as specified. Be sure to include your SPECTRE input files for the project.

~~A timing diagram you should use to test the neuron will be provided in several days.~~

Here is the order of inputs and outputs you should use to test your circuit. The output is directly under the input. The earliest input is on the left:

Input: 0(first)0011111000110010000101010(last)

Output:0(first)0000111000000010000000010(last)

Be sure to also demonstrate that load and reset perform as specified.

Lab Report Contents:

A cover sheet (title page) giving your name, date you submitted the lab, title, and student number
A description of the neuron you built, including a transistor-level or gate-level circuit diagram printed from Cadence, and a description of how your circuit remembers past inputs.
A floorplan of the neuron layout. A floorplan shows where on the layout you placed functions, without showing the details of the functions. Cadence might have a tool to do this for you.
Your neuron layout and neuron layout simulation results as images. Make sure the layout and simulation images are of high enough resolution so that we can zoom in to check things.
A description of the simulation experiments you ran with SPECTRE for the neuron.
SPECTRE netlist files for both schematic and layout of the neuron, generated by Cadence, which will include the technology file, the input stimulus file and the circuitry netlist.
SPECTRE outputs (waveforms) for the neuron schematic and layout.
High resolution images of your neuron layout.

Items 1-5 and 7-8 should all be in a single report. Tar this report along with the files specified in item 6, and upload to the assignments page of the blackboard.

IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar file, uploaded to blackboard. Files uploaded to the dropbox will not be graded. All layouts must be in color. Failure to follow these instructions could result in deduction of points.