Homework Assignment #5
Spring 2012 EE 477
Due April 10, 2012 11:59 PM, online
Solutions will be posted morning of April 11
Assume lambda is .1 microns. Assume Vdd is 1.8v. Tox = 57 angstroms for thinox, and 5000 angstroms for thick oxide. Metal thickness is .5 microns. You can use these values for transistor betas: βn (beta)= 219.4 W/L μ A(microamps)/V2 and βp (beta)= 51 W/L μ A/V2 .
1)a) (10%) Compute for the compound gate in Homework Assignment #4 of Spring 2012 the worst-case falling RC time constant at the output using a lumped model, in terms of terms of Rchn, Cdp and Cdn.
(b) (10%) Compute the worst-case falling RC time constant at the output using an Elmore delay model, in terms of the variables given above.
2)a) (10%) Connect an output of a 2-input NAND through a long wire to the input of a second 2-input NAND. For the NANDs, assume Rchn=1000 ohms and Rchp = 4000 ohms, Cgn=Ggp=Cdn=Cdp=10 ff. For the wire assume Rw= 100 ohms and Cw = 6ff. Compare the rise and fall times at the input to the second NAND using Elmore delay model. Use π-model for the wire.
b) (10%) Insert a pair of inverters 1/3 and 2/3 of the way along the wire. Compare the fall time constant at the output of the second NAND to the fall time constant at the the input of the pair of inverters. Use the Elmore delay model. Also compare to the results of part a.
b) (10%) Insert a pair of inverters 1/3 and 2/3 of the way along the wire. Compare the fall time constant at the input of the second NAND to the fall time constant at the the input of the pair of inverters. Use the Elmore delay model. Also compare to the results of part a.
3) (15%) Assume a flipflop like the one you are building in lab 2. What are the factors that affect the total clock period (clock cycle), divided into times before and after the falling clock. Factors include capacitances, resistances, and any safety margins due to early and late clocks.
4) (10%) Use a chain of inverters to drive a 16 pF load. How many stages (n) are required in the inverter chain, assuming the first stage is an inverter with unit transistors, assuming equal delay in all stages, and assuming Cg(n+p) for the first inverter in the chain = 14 ff? You can assume Cd(source or drain) = 2* Cgn = 2 *Cgp. How much wider (a) are the transistors in each stage than the previous stage?
5) (10%). Compute the fall time at the output of an inverter with NMOS transistor width 8 lambda, and length minimum length. Assume CL = 20 ff.
6) (10%). Assume a wire is 180 microns long. Assume R/micron = .2 ohms, and C/micron = 20 ff. Compute the wire delay the most accurate way possible.
7) (10 %) For the network of gates shown on page 20-2 of Lecture 20, compute the total longest delay through the network starting with the rise time at the output of gates 1 and 5. Assume Cd = 2Cg.
8) (5 %) A wire stretches 2.6cm across a CMOS chip. Assuming electrons move at .00025 m/sec , what is the fastest rise/fall time on the wire that we can have without being forced to consider inductance?