Homework Assignment #4

due 4/3/2012 In the boxes in EEB at 5 PM or

online using the DEN assignments function at 11:59 PM

Assume for the problems below that

V_dd= 1.8 V, V_tp = - 0.4 V, V_tn = 0.4 V, V_tp,BE = - 0.5 V, and V_tn,BE = 0.5 V.

T_ox = 41 angstroms for thinox, and 5000 angstroms for thick oxide.

ε₀ (epsilon) = 8.85 X 10 ^-14 F/cm and ε_oxide(epsilon) = 3.9.

lambda = 0.1 micron.

C_jbsn = 9.725 x 10^-4 pF/ μm² and C_jbswn = 2.27 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

C_jbsp = 11.57 x 10^-4 pF/ μm² and C_jbswp = 1.8 x 10^-4 pF/ μm (micrometer). Assume drain is the same.

x_j (diffusion depth) = 0.1 microns.

Assume ß_n (k_n)= 219.4 W/L µ A(microamps)/V² and ß_p (k_p)= 51 W/L µ A/V²

^{1. (15%) Use the compound gate shown here. Label the sources and drains of all transistors. Show an identical Euler path for both NMOS and PMOS transistors by listing transistor inputs on both paths.}

^{2. (20%) Give a stick diagram for the compound gate in Problem 1 above, using the Euler path you found.}

^{3. (10%) Size the devices in the longest paths in the compound gate to give equal rise and fall times in the worst case.}

^{4. (10%)} How many diffusion capacitances get charged/discharged in the worst case, assuming no diffusion regions are shared?

^{5. (15%) A design has a number of common inputs/outputs that need to be connected. Use the left edge algorithm to connect common inputs using as few tracks as possible. The starting and ending positions of each common input are given below. You can assume the inputs come from either the top or the bottom of the channel to make the problem easier.}

^{A (3,10)}

^{B (2,4)}

^{C (11,17)}

^{D (11,14)}

^{E (5,9)}

^{F( 9,12)}

^{G (1,4)}

^{H (6,10)}

^{I (4,8)}

^{6. (10%) Compute the gate capacitance of a PMOS transistor that is unit length and twice unit width.}

^{7. (10%) Compute the source diffusion capacitance of a minimum size NMOS transistor.}

^{8. (10%)} Use the Fringing Field Capacitance graph shown on p.247 of the text. Approximate the total capacitance of a metal1 wire by first computing the parallel plate capacitance then using the graph to approximate total capacitance. Assume the metal thickness is 1 μm. The metal is 5 lambda wide, and 50 lamda long. Assume the metal is over the substrate with no other layers in between except the SiO₂ insulation.