Homework Assignment #1
EE 477 Spring 2012 Professor Parker
Hardcopies due in the course boxes on the third floor of EEB 5 PM 1/26/12
Ecopies due 11:59 PM 1/26/12 using the "Assignment" Function on DEN
To ensure academic privacy, please use a cover page on your homework hard copies that does not contain any work.
1. (7%) Give the Boolean expression for a four-bit magnitude comparator computation with output C and inputs X (X0, X1, X2, X3) and Y (Y0, Y1, Y2, Y3.) X and Y are being compared. C is high (1) when X is greater than Y, and low (0) otherwise. X0 and Y0 are the least significant bits respectively.
2. (8%) Show an implementation of the comparator computation in Problem 1 at the gate level using complementary NAND, NOR and INV gates. You may not use XOR or XNOR gates.
Note: You must invert inputs if you need the complements of the inputs in the circuit. You can use gates with any number of inputs.
3. (15%) Show an implementation of the four-bit comparator from Problem 2 at the circuit (transistor) level (for an example of complementary CMOS NAND gates and inverter, see Fig. 1 for example. ) You do not need to show the transistor level for identical gates. If you use 3 2-input NAND gates, you only need to show one of them.
4. (10%) Show a compound gate implementation of the comparator at the circuit (transistor) level, similar to the compound gate shown in Fig. 2. You may need an additional inverter at the output of a compound gate and additional inverters at the inputs to get correct results. Compare the number of transistors to the original design in Problem 3.
5. (15%) Show compound gate implementations for /F= ((A+B)’(C+D)’(E+F+GH(I+J))’. ’ indicates complement.
6. (10%) Show a design at the transistor level of a 7-input mux. Use only NOR gates and inverters.
7. (10%) Design a latch at the gate and transistor level that has two possible data inputs (D0 and D1) plus the feedback path (Q). Select picks one of the two data inputs. The latch should load when clock is high. The latch can be asynchronously Reset anytime and synchronously Set when clock is high. Set means the output of the latch that is inverted and fed back to the mux, Q, is high, and reset means the output is low. The 3-input MUX used in the latch should be constructed using transmission gates. Please clearly mark the inputs (D0, and D1), controls (select, set and reset), clock and outputs (Q and ~Q) on the circuit diagram.
8. (15%) Show the stick diagram of the latch designed in Problem 7.
9. (10%) Make a directory (folder) on your UNIX account that is called HW1. Create a small file on your UNIX account that contains your full name on the first line and your student number on the second line. Use EMACS or any other unix editor to create the file. Save the file in the HW1 directory as yourlastname.txt. Change the directory to HW1. Give the results of typing the command ls -l yourlastn* , leaving off the last three letters of your last name. If your last name is two words with a space in between, use the last word.